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mc81f4 104 october 19, 2009 ver. 1.35 1 abov semiconductor 8 - bit single - chip microcontrollers mc8 1 f 4 1 04 mc81f4 1 04 m /b/s users manual (ver. 1. 3 5 )
mc81f4 104 2 october 19, 2009 ver. 1.35 version 1.35 published by fae team ?
mc81f4 104 october 19, 2009 ver. 1.35 3 revision history version 1.3 5 ( o c t o b e r 1 9 , 2009 ) this book c h a n g e e v a . b o a r d p i c t u r e . ( t h e b o a r d ? s c o l o r i s c h a n g e d f r o m b l u e t o g r e e n ) version 1.34 ( september 30, 2009 ) add more tools at 1.3 development tools . version 1.33 ( september 18, 2009 ) remove rising /falling time at lvr electrical ch aracteristics. change ? 1.83v ? to por level in por description. add por level at dc characteristics . add rom option read timing information. add typical characteristics . version 1.2 2 ( july 7, 2009 ) 23.3 hardware conditions to enter the isp mode is updated. note of r03 port control register is updated. version 1.2 1 ( june 29, 2009 ) 8 sop ordering name is changed from mc81f4104d to MC81F4104M . version 1.2 ( june 29 , 2009 ) remove ? wdt ? at stop release description . ? wdt ? is not a release source of stop mode. version 1. 1 ( june 1 7 , 2009 ) add rom writing endurance at features. version 1.0 ( june 15, 2009 ) remove preliminary . some errata are fixed. remove (or 16b i t *1ch) at timer clause of the feature page. version 0 . 9 preliminary ( april 16, 2009 ) add a sub - chapter ? changing the stabilizing time ? at the chapter ? power down operation ? . add a note for r00/r01 ports after r0conh description. one of bit ? s clock source ? 2048 ? is changed to ? 1024 ? . version 0 . 8 preliminary ( april 8, 2009 ) description of isp chapter is updated. operation range is changed.( 2.0v~5.5v > 2.2v~5.5v)
mc81f4 104 4 october 19, 2009 ver. 1.35 version 0 . 7 preliminary ( april 1, 2009 ) chapter ? 7.electrical characteristics ? is updated. version 0 . 6 preliminary ( march 5, 2009 ) correct pin m ap diagram in the chapter ? 22.emulator ? . move the sclk pin for isp is moved to r04 port. note for adc recommended circuit is changed. version 0 . 5 preliminary ( february 12, 2009 ) update the chapter ? 6. port structure ? . update the chapter ? 7. electrical characteristics ? . update the chapter ? 23. in system programming ? . version 0 . 4 preliminary ( december 19 , 2008) block diagrams of timer 2/3 and pwm are corrected. version 0 . 3 preliminary ( december 8 , 2008) operating voltage changed (2.2v~5.5v 2.0v~5.5v) version 0 . 2 preliminary ( november 17 , 2008) s ome errata are corrected . version 0 . 1 preliminary ( november 14 , 2008) s ome errata are corrected . version 0 .0 preliminary ( november 12 , 2008)
mc81f4 104 october 19, 2009 ver. 1.35 5 table of contents revision history ................................ ................................ ................................ .............................. 3 table of contents ................................ ................................ ................................ .......................... 5 1. overview ................................ ................................ ................................ ................................ ......... 8 1.1 description ................................ ................................ ................................ ................................ .... 8 1.2 features ................................ ................................ ................................ ................................ ........ 8 1.3 development tools ................................ ................................ ................................ ....................... 9 1.4 ordering information ................................ ................................ ................................ ................... 10 2. block diagram ................................ ................................ ................................ ............................ 11 3. pin assignmen t ................................ ................................ ................................ ........................... 12 3.1 10 pin - ssop ................................ ................................ ................................ .............................. 12 3.2 8 pin - pdip/sop ................................ ................................ ................................ ......................... 12 3.3 summary ................................ ................................ ................................ ................................ ..... 13 4. package diagram ................................ ................................ ................................ ....................... 14 4.1 10 ssop - mc81f4104s ................................ ................................ ................................ ........... 14 4.2 8 pdip - mc81f4104b ................................ ................................ ................................ ............... 15 4.3 8 sop - MC81F4104M ................................ ................................ ................................ ............... 16 5. pin des cription ................................ ................................ ................................ ........................... 17 6. port stucture ................................ ................................ ................................ ............................ 18 7. electrical characteristics ................................ ................................ ................................ . 20 7.1 absolute maximum ratings ................................ ................................ ................................ ........ 20 7.2 recommended operating conditions ................................ ................................ ........................ 20 7.3 a/d converter characteristics ................................ ................................ ................................ .... 21 7.4 dc electrical characteristics ................................ ................................ ................................ ...... 22 7.5 input/output capacitance ................................ ................................ ................................ ........... 23 7.6 serial electric characteristics ................................ ................................ ................................ ..... 23 7.7 data retention voltage in stop mode ................................ ................................ ........................ 24 7.8 lvr (low voltage reset) electrical characteristics ................................ ................................ .. 24 7.9 main clock osc illator characteristics ................................ ................................ .......................... 25 7.10 external rc oscillation characteristics ................................ ................................ .................... 26 7.11 internal rc oscillation characteristics ................................ ................................ ..................... 27 7.12 main oscillation stabilization time ................................ ................................ ........................... 27 7.13 operating voltage range ................................ ................................ ................................ ......... 28 7.14 typical characteristics ................................ ................................ ................................ .............. 29 8. rom option ................................ ................................ ................................ ................................ ... 33 8.1 rom option ................................ ................................ ................................ ................................ . 33 8.2 read timing ................................ ................................ ................................ ................................ 34 9. memory organi zation ................................ ................................ ................................ .............. 35 9.1 registers ................................ ................................ ................................ ................................ ..... 35 9.2 program memory ................................ ................................ ................................ ........................ 39 9.3 data memory ................................ ................................ ................................ .............................. 42 9.4 user memory ................................ ................................ ................................ .............................. 42 9.5 stack area ................................ ................................ ................................ ................................ .. 42 9.6 control registers ( sfr ) ................................ ................................ ................................ ........... 42 9.7 addressing modes ................................ ................................ ................................ ...................... 45 10. i/o ports ................................ ................................ ................................ ................................ ...... 53
mc81f4 104 6 october 19, 2009 ver. 1.35 10.1 r0 port registers ................................ ................................ ................................ ..................... 53 11. interr utp controller ................................ ................................ ................................ .......... 57 11.1 registers ................................ ................................ ................................ ................................ ... 58 11.2 interrupt sequence ................................ ................................ ................................ ................... 60 11.3 brk interrupt ................................ ................................ ................................ ............................ 62 11.4 multi interrupt ................................ ................................ ................................ ............................ 62 11.5 interrupt vector & priority table ................................ ................................ ............................... 63 12. external interrupts ................................ ................................ ................................ ............. 64 12.1 registers ................................ ................................ ................................ ................................ ... 64 12.2 procedure ................................ ................................ ................................ ................................ . 65 13. oscillation circuits ................................ ................................ ................................ .............. 66 13.1 main oscillation circuits ................................ ................................ ................................ ........... 66 13.2 pcb layout ................................ ................................ ................................ ............................... 67 14. basic interval timer ................................ ................................ ................................ ............... 68 14.1 registers ................................ ................................ ................................ ................................ ... 69 15. watch dog timer ................................ ................................ ................................ ...................... 70 15.1 registers ................................ ................................ ................................ ................................ ... 71 16. timer 2 ................................ ................................ ................................ ................................ ............ 72 16.1 registers ................................ ................................ ................................ ................................ ... 72 16.2 timer 2 8 - bit mode ................................ ................................ ................................ ................... 74 17. time r 3 ................................ ................................ ................................ ................................ ............ 76 17.1 registers ................................ ................................ ................................ ................................ ... 76 17.2 timer 3 8 - bit mode ................................ ................................ ................................ ................... 78 18. high speed pwm ................................ ................................ ................................ ............................ 80 18.1 registers ................................ ................................ ................................ ................................ ... 82 19. 12 - bit adc ................................ ................................ ................................ ................................ ..... 83 19.1 registers ................................ ................................ ................................ ................................ ... 84 19.2 procedure ................................ ................................ ................................ ................................ . 85 19.3 conversion timing ................................ ................................ ................................ .................... 85 19.4 internal reference voltage levels ................................ ................................ ........................... 86 19.5 recommended circuit ................................ ................................ ................................ .............. 86 20. reset ................................ ................................ ................................ ................................ ............ 87 20.1 reset process ................................ ................................ ................................ .......................... 87 20.2 reset sources ................................ ................................ ................................ .......................... 88 20.3 external reset ................................ ................................ ................................ .......................... 88 20.4 watch d og timer reset ................................ ................................ ................................ ........... 88 20.5 power on reset ................................ ................................ ................................ ....................... 89 20.6 low voltage reset ................................ ................................ ................................ .................... 89 21. power down operation ................................ ................................ ................................ ........ 90 21.1 sleep mode ................................ ................................ ................................ ............................... 90 21.2 stop mode ................................ ................................ ................................ ................................ . 92 21.3 sleep vs stop ................................ ................................ ................................ ............................ 95 21.4 changing the stabilizing time ................................ ................................ ................................ .... 96 21.5 minimizing current consumption ................................ ................................ ............................. 96 22. emulator ................................ ................................ ................................ ................................ .... 98 23. in system programming ................................ ................................ ................................ ...... 101 23.1 getting started ................................ ................................ ................................ ........................ 101 23.2 basic isp s/w information ................................ ................................ ................................ ..... 102
mc81f4 104 october 19, 2009 ver. 1.35 7 23.3 hardware conditions to enter the isp mode ................................ ................................ .......... 104 23.4 entering isp mode at power on time ................................ ................................ ...................... 105 23.5 usb - sio - isp board ................................ ................................ ................................ ............... 106 24. instruction set ................................ ................................ ................................ ...................... 107 24.1 terminology list ................................ ................................ ................................ ..................... 107 24.2 instruction map ................................ ................................ ................................ ....................... 108 24.3 instruction set ................................ ................................ ................................ ......................... 109
mc81f4 104 8 october 19, 2009 ver. 1.35 mc 81 f 4 1 04 8 bit mcu with 1 2 - bit a/d converter 1. overview 1.1 description mc81f 4 1 04 is a cm os 8 bit mcu which provides a 4 k bytes flash - rom and 192 bytes ram. it has following major features, 12 bit adc : it has 7(5) ch a/d converter which can be used to measure minute electronic voltage and currents. 810 core : same with abov ? s 800 core but twice faster. 800 core use a divided system clock but 810 core use the system clock directly 1.2 features rom(flash) : 4k bytes (endurance: 100 cycle) sram : 192 bytes minimum instruction execution time 166 n sec at 12 mhz (nop instruction) 1 2 - bit a/d converter : 7 ch general purpose i/o(gpio) 10 - pin pkg : 8 8 - pin pkg : 6 timer/counter 8bit x 2ch pwm 10 bit high speed pwm * 1ch watchdog timer (wdt) : 8bit x 1 ch basic interval timer(bit) : 8bit x 1ch interrupt source : 9 ch external interrupt s : 3 ch timer 2/3 match/overflow wdt, bit p ower on reset (por) low voltage reset (lvr) 4 level detector (2.4/2.7/3.0/4.0v) power down mode stop mode sleep mode operating voltage & frequency 4. 0 v C 5.5v (at 1.0 C 12 .0 mhz) 2.7 v C 5.5v (at 1.0 C 8 .0 mhz) 2. 2 v C 5.5v (at 1.0 C 4.2 mhz) operating temperature - 40c ~ 85c oscillator type crystal , ceramic , rc for main clock internal oscillator ( 8mhz/ 4mhz/2mhz /1mhz ) package 10 ssop , 8 pdip/sop available pb free package
mc81f4 104 october 19, 2009 ver. 1.35 9 1.3 development tools the mc8 1 f 4 1 04 is supported by a full - featured macro assembler, c - compiler, an in - circuit emulator choice - dr. tm , falsh programmers and isp tools . there are two different type of programmers such as si ngle type and gang type. for mo r e detail, macro assembler operates un der the ms - windows 95 and up versioned windows os. and hms800c compil er only operates under the ms - windows 2000 and up ver sioned windows os. please contact sales part of abov semiconductor. and you can see more information at ( http://www.abov.co.kr ) figure 1 - 1 pgmplususb ( single writer ) figure 1 - 2 sio isp ( in system programmer ) figure 1 - 3 standalone isp (vdd power is not supplied) figure 1 - 4 ez - isp (vdd supplied standalone type isp) figure 1 - 5 standalone gang4 ( for mass production ) figure 1 - 6 standalone gang 8 ( for mass production ) figure 1 - 7 choice - dr ( emulator )
mc81f4 104 10 october 19, 2009 ver. 1.35 1.4 ordering information device name flash rom ram package mc81f4104 m 4k bytes 192 bytes 8_sop mc81f4104b 8_pdip mc81f4104s 10_ssop
mc81f4 104 october 19, 2009 ver. 1.35 11 2. block diagram figure 2 - 1 system block diagram r e s e t p o r t i / o a n d e x t e r r u p t c o n t r o l 4 k x 8 - b i t r o m 8 - b i t t i m e r / c o u n t e r 2 h i g h s p e e d p w m 8 - b i t t i m e r / c o u n t e r 3 a / d c o n v e r t e r p o r t 0 g 8 1 0 c p u 1 9 2 x 8 - b i t r a m a n 0 / x i n / r 0 0 a n 1 / x o u t / r 0 1 a n 2 / r 0 2 a n 4 / r 0 4 / p w m 2 o / e x t 0 / t 2 o a n 5 / r 0 5 a n 6 / r 0 6 / e c 2 / e x t 1 a n 7 / r 0 7 / v r e f / e c 3 / e x t 2 x i n x o u t v d d v s s e x t 1 / a n 6 / r 0 6 / e c 2 a n 4 / r 0 4 / p w m 2 o / t 2 o / e x t 0 a n 4 / r 0 4 / p w m 2 o / t 2 o / e x t 0 a n 7 / r 0 7 / v r e f / e x t 2 / e c 3 x i n / a n 0 / r 0 0 x o u t / a n 1 / r 0 1 a n 2 / r 0 2 r e s e t b / r 0 3 t 2 o / e x t 0 / p w m 2 o / a n 4 / r 0 4 a n 5 / r 0 5 e c 2 / e x t 1 / a n 6 / r 0 6 e c 3 / e x t 2 / v r e f / a n 7 / r 0 7 l v r ( p o r ) b a s i c t i m e r / w a t c h d o g t i m e r
mc81f4 104 12 october 19, 2009 ver. 1.35 3. pin assignmen t 3.1 1 0 pin - ssop 3.2 8 pin - p di p/sop 7 6 9 8 1 0 r 0 4 / a n 4 / p w m 2 o / e x t 0 / t 2 o ( s c l k ) r 0 7 / a n 7 / v r e f / e c 3 / e x t 2 v d d r 0 6 / a n 6 / e c 2 / e x t 1 ( s d a t a ) r 0 5 / a n 5 r 0 2 / a n 2 1 2 3 4 5 v s s x i n / r 0 0 / a n 0 x o u t / r 0 1 / a n 1 v p p / r e s e t b / r 0 3 m c 8 1 f 4 1 0 4 5 7 6 8 r 0 4 / a n 4 / p w m 2 o / e x t 0 / t 2 o ( s c l k ) r 0 7 / a n 7 / v r e f / e c 3 / e x t 2 v d d r 0 6 / a n 6 / e c 2 / e x t 1 ( s d a t a ) 1 2 3 4 v s s x i n / r 0 0 / a n 0 x o u t / r 0 1 / a n 1 v p p / r e s e t b / r 0 3 m c 8 1 f 4 1 0 4
mc81f4 104 october 19, 2009 ver. 1.35 13 3.3 summary alternative functions pin number pin status at reset 1 0pin 8 pin r00 an 0 / xin 2 2 input r01 an1/ xout 3 3 input r02 an 2 4 x open - drain output r03 v pp/resetb 5 4 input r04 an4 / ext 0 /pwm2 o/t2o 6 5 input r05 an 5 7 x open - drain output r06 an6 / ext 1 /ec2 8 6 input r07 an7 / ext 2 /vref/ec3 9 7 input vdd - 10 8 - vss - 1 1 - note : some pins are initialized by open - drain out put mode, when the device is reset. because the pins are hided in 8 pin package and it is stable that hided pins are be in open - drain - output mode.
mc81f4 104 14 october 19, 2009 ver. 1.35 4. package diagram 4.1 10 ssop - mc81f4104s
mc81f4 104 october 19, 2009 ver. 1.35 15 4.2 8 pdip - mc81f4104b
mc81f4 104 16 october 19, 2009 ver. 1.35 4.3 8 so p - mc81f4104 m
mc81f4 104 october 19, 2009 ver. 1.35 17 5. pin description pin names i/o pin description alternative functions r00 i/o this port is a 1 - bit programmable i/o pin . schmitt trigger input, push - pull , or open - drain output port. when used as an input port, a p ull - up resistor can be specified in 1 - bit . xin/an0 r01 xout/an1 r02 an2 r03 resetb r04 pwm2o/t2o/ an4/ ext 0 r05 an5 r06 ec2/an6/ ext 1 r07 ec3/vref/an7/ ext 2 ext 0 i/o external interrupt input/timer 2 capture input r04/pwm2o/ t2o/an4 ext 1 i/o external interrupt input r06/ec2/an6/ ext 2 i/o external interrupt input/timer 3 capture input r07/ec3/vref/ an7 t2o i/o timer 2 clock output r04/pwm2o/ an4/ ext 0 ec2 i/o timer 2 event count input r06/an6/ ext 1 pwm2o i/o pwm 2 clock output r04/t2o/ an4/ ext 0 ec3 i/o timer 3 event count input r07/vref/an7/ ext 2 an0 i/o adc input pins r00/xin an1 r01/xout an2 r02 an4 r04/pwm2o/ t2o/ ext 0 an5 r05 an6 r06/ec2/ ext 1 an7 r07/ec3/vref/ ext 2 resetb i system reset pin r03 x in C main oscillator pins r00/an0, x out r01/an1 v dd C power input pins C v ss C v ref C a/d converter reference voltage r07/an7/ec3/ ext 2
mc81f4 104 18 october 19, 2009 ver. 1.35 6. p ort st ucture r03/resetb input/output data clock adc r00 xin an0 r01 xout an1 r00/xin, r01/xout o u t p u t d a t a o u t p u t d i s a b l e i / o i n t e r n a l r e s e t l v r e n i n p u t d a t a l v r e n v d d o p e n - d r a i n * o u t p u t d a t a * o u t p u t d i s a b l e v d d p u l l - u p e n a b l e i / o * a d c * * i n p u t d a t a * a d c e n a b l e a d c s e l e c t x i n / x o u t o s c s
mc81f4 104 october 19, 2009 ver. 1.35 19 input/output data input data output data adc r02 - - an2 r04 ext0 pwm2o/t2o an4 r05 - - an5 r06 ext1/ec2 - an6 r07 ext2/ec3 - an7/vref v d d o p e n - d r a i n * o u t p u t d a t a * o u t p u t d i s a b l e v d d p u l l - u p e n a b l e i / o * a d c * * i n p u t d a t a * a d c e n a b l e a d c s e l e c t
mc81f4 104 20 october 19, 2009 ver. 1.35 7. electrical characteristics 7.1 absolute maximum ratings parameter symbol ratings unit note supply voltage vdd - 0.3 C +6. 0 v C normal voltage pin vi - 0.3 C vdd+0.3 v voltage on any pin with respect to vss vo - 0.3 C vdd+0.3 v ioh - 10 ma maximum current output sourced by (ioh per i/o pin) ioh - 80 ma maximum current (ioh) iol 20 ma maximum current sunk by (iol per i/o pin) iol 160 ma maximum current (iol) total power dissipation fxin 600 mw C storage temperature tstg - 65 C +150 c C note : stresses above those listed under absolute maximum ratings may cause permanent damage to the device. this is a stress rating only and functional operation of the device at any other conditions above those indicated in the operational sections of this specification is not implied. exposure to absolute maximum rating conditions for ext ended periods may affect device reliability. 7.2 recommended operating conditions (t a = - 40 ? c to + 85 ? c) parameter symbol conditions min max units fx = 1.0 C C C C
mc81f4 104 october 19, 2009 ver. 1.35 21 7.3 a/d converter characteristics ( t a = - 40 ? c to + 85 ? c, v ref = 2. 7 v to 5.5 v ) parameter symbol conditions min typ max units a/d converting resolution C C C 12 C bits integral linearity error ile vref = 5.12v, v ss = 0v, t a = + 25 ? c C C ? lsb differential linearity error dle C C ? offset error of top eot C ? offset error of bottom eob C ? overall accuracy C C conversion time t conv C 25 C C ? s analog input voltage vain C v ss C vref v analog reference voltage vref C 2.7 C 5.5 v analog input current i ain vdd = vref = 5v C C 10 ? a analog block current iavdd vdd = vref = 5v C 1 3 ma vdd = vref = 3v C 0.5 1.5 vdd = vref = 5v power down mode C 100 500 na bgr - vdd = 5v, t a = + 25 ? c - 1.67 - v - vdd = 4v, t a = + 25 ? c - 1.63 - - vdd = 3v, t a = + 25 ? c - 1.62 -
mc81f4 104 22 october 19, 2009 ver. 1.35 7.4 dc electrical characteristics (t a = - 40 ? c to + 85 ? c, v dd = 2. 2 C 5.0 v , vss=0v, f xin =12mhz) parameter symbol conditions min typ max units input high voltage vih1 r0 , v dd = 4.5v C C C C C C C C C C C C C C C C C C C C C C C ? ? ? C C C C ? C
mc81f4 104 october 19, 2009 ver. 1.35 23 7.5 input/output capacitance (t a = - 40 ? c to + 85 ? c, v dd = 0 v) parameter symbol conditions min typ max units input capacitance cin f=1mhz unmeasured pins are connected vss C C 7.6 serial electric characteristics (t a = - 40 ? c to + 85 ? c, v dd = 2. 2 v to 5.5 v) parameter symbol conditions min typ max units interrupt input, high, low width t inth , t intl all interrupt, v dd = 5 v 200 C C C C 7 - 1 input timing for external interrupt figure 7 - 2 input timing for resetb external interrupt 0.8 v dd 0.2 v dd t inth t inth resetb 0 . 2 v dd t rsl
mc81f4 104 24 october 19, 2009 ver. 1.35 7.7 data retention voltage in stop mode (t a = - 40 ? c to + 85 ? c, v dd = 2. 2 v to 5.5 v) parameter symbol conditions min typ max units data retention supply voltage v dddr C C ? C C 7.8 lvr (low v o ltage r e set) electrical characteristics (t a = - 40 ? c to + 85 ? c, v dd = 2.2 v to 5.5 v) figure 7 - 3 stop mode release timing when initiated by an interrupt figure 7 - 4 stop mode release timing when initiated by resetb i d l e m o d e ( w a t c h d o g t i m e r a c t i v e ) v d d n o t e : t w a i t i s t h e s a m e a s 2 5 6 x 1 / b t c l o c k i n t r e q u e s t e x e c u t i o n o f s t o p i n s t r u c t i o n ~ ~ d a t a r e t e n t i o n ~ ~ s t o p m o d e n o r m a l o p e r a t i n g m o d e 0 . 8 v d d t w a i t v d d d r v d d n o t e : t w a i t i s t h e s a m e a s 2 5 6 x 1 0 2 4 x 1 / f x x ( 6 5 . 5 m s @ 4 m h z ) r e s e t b e x e c u t i o n o f s t o p i n s t r u c t i o n ~ ~ d a t a r e t e n t i o n ~ ~ s t o p m o d e o s c i l l a t i o n s t a b i l l i z a t i o n t i m e n o r m a l o p e r a t i n g m o d e t w a i t r e s e t o c c u r s 0 . 2 v d d v d d d r 0 . 8 v d d
mc81f4 104 october 19, 2009 ver. 1.35 25 parameter symbol conditions min typ max units lvr voltage vlvr C C C C notes: 1. the c urrent of lvr circuit is consumed when lvr is enabled by rom option . 2. 2 16 /fx ( = 6.55 ms at fx = 10 mhz ) 7.9 main clock oscillator characteristics (t a = - 4 0 ? c to + 85 ? c, v dd = 2. 2 v to 5.5 v) oscillator parameter conditions min typ. max units crystal main oscillation frequency 2.2 v C C C C C C C C C C C C C C C C C C figure 7 - 5 crystal/ceramic oscillator c1 c2 x in x out
mc81f4 104 26 october 19, 2009 ver. 1.35 7.10 external rc oscillation characteristics (t a = - 4 0 ? c to + 85 ? c, v dd = 2. 2 v to 5.5 v) parameter symbol conditions min typ. max units rc oscillator freque - ncy range (1) ferc t a = 25 ? C ? C C C ? ? C C a = 25 ? C C notes: 1. the external resistor is connected between v dd and x in pin and the 270pf capacitor is connected between x in and v ss pin . (x out pin can be used as a normal port). the frequency is adjusted by external resistor. 2. the min/max frequencies are with in the range of rc osc frequency ( 1mhz to 8mhz) 3. data based on characterization resul ts, not tested in production figure 7 - 6 external clock figure 7 - 7 external clock x in x out x in r v dd v ss 270pf
mc81f4 104 october 19, 2009 ver. 1.35 27 7.11 in ternal rc oscillation characteristics (t a = - 40 ? c to + 85 ? c, v dd = 2. 2 v to 5.5 v) parameter symbol conditions min typ. max units rc oscillator frequency (1) firc v dd = 5.5 v, t a = 25 ? C ? ? C ? C C notes: 1. data based on characterization results, not tested in production 2. x in and x out pins can be used as i/o ports. 7.12 main oscillation stabilization time (t a = - 4 0 ? c to + 85 ? c, v dd = 2. 2 v to 5.5 v) oscillator conditions min typ. max units crystal fx > 1 mhz oscillation stabilization occurs when v dd is equal to the minimum oscillator voltage range. C C C C C figure 7 - 8 clock timing measurement at xin x in 0 . 8 v dd 0 . 2 v dd t xh t xl 1 / fx
mc81f4 104 28 october 19, 2009 ver. 1.35 7.13 operating voltage range figure 7 - 9 operating voltage range 2 . 2 1 . 0 m h z 4 . 0 5 . 5 . 8 . 0 m h z 1 2 . 0 m h z ( m a i n o s c f r e q u e n c y ) 2 . 7 s u p p l y v o l t a g e ( v ) 4 . 2 m h z
mc81f4 104 october 19, 2009 ver. 1.35 29 7.14 typical characteristics these graphs and tables provided in this section are for design guidance only and are not tested or guaranteed. in some graphs or tables the data presented are outside specified operating range (e.g. outside specified vdd range). this is for information on ly and devices are guaranteed to operate properly only within the specified range. the data presented in this section is a statistical summary of data collected on units from different lots over a period of time. typical represents the mean of the distribution while max or min represents (mean + 3 ) and (mean ? 3 ) respectively where is standard deviation . figure 7 - 10 i dd C v dd in normal mode figure 7 - 11 i sleep C v dd in sleep mode figure 7 - 12 i stop C v dd in stop mode 0 1 2 3 4 5 6 7 2.5v 3v 3.5v 4v 4.5v 5v 5.5v ma 0.0 0.2 0.4 0.6 0.8 1.0 1.2 1.4 2.5v 3v 3.5v 4v 4.5v 5v 5.5v ma 0.00 0.05 0.10 0.15 0.20 0.25 2.5v 3v 3.5v 4v 4.5v 5v 5.5v ua
mc81f4 104 30 october 19, 2009 ver. 1.35 figure 7 - 13 i oh - v oh at v dd =5v figure 7 - 14 i o l - v o l at v dd =5v - 20 - 18 - 16 - 14 - 12 - 10 - 8 - 6 - 4 - 2 0 2v 2.5v 3v 3.5v 4v 4.5v 4.99v - 40 c 25 c 85 c ma 0 2 4 6 8 10 12 14 16 18 0v 0.23v 0.47v 0.70v - 40 c 25 c 85 c ma
mc81f4 104 october 19, 2009 ver. 1.35 31 figure 7 - 15 v ih1 - v dd figure 7 - 16 v i l 1 - v dd figure 7 - 17 v ih 2 - v dd figure 7 - 18 v i l2 - v dd 1.0 v 1.5 v 2.0 v 2.5 v 3.0 v 3.5 v 4.0 v 2.7v 3.3v 4.5v 5.5v vih1 1.0 v 1.5 v 2.0 v 2.5 v 3.0 v 3.5 v 4.0 v 2.7v 3.3v 4.5v 5.5v vil1 1.0 v 1.5 v 2.0 v 2.5 v 3.0 v 3.5 v 4.0 v 2.7v 3.3v 4.5v 5.5v vih3 1.0 v 1.5 v 2.0 v 2.5 v 3.0 v 3.5 v 4.0 v 2.7v 3.3v 4.5v 5.5v vil3
mc81f4 104 32 october 19, 2009 ver. 1.35 figure 7 - 19 8mhz internal osc freq. - v dd figure 7 - 20 ext . r/c osc freq. - v dd at 25 figure 7 - 21 ext . r/c osc freq. - v dd at 85 figure 7 - 22 ext . l r/c osc freq. - v dd at - 40 0 1 2 3 4 5 6 7 8 9 10 2.7v 3.0v 3.3v 3.5v 4.0v 4.5v 5.0v 5.5v 6.0v mhz - 40 85 25 0 2 4 6 8 10 12 14 16 18 20 2.2v 2.5v 3.0v 3.5v 4.0v 4.5v 5.0v 5.5v 6.0v mhz 5.1 ? 12.0 ? 19.7 ? 39.4 ? 61.2 ? 81.0 ? 97.5 ? 122.0 ? 147.2 ? 198.9 ? 339.0 ? 0 2 4 6 8 10 12 14 16 18 20 2.2v 2.5v 3.0v 3.5v 4.0v 4.5v 5.0v 5.5v 6.0v mhz 5.1 ? 12.0 ? 19.7 ? 39.4 ? 61.2 ? 81.0 ? 97.5 ? 122.0 ? 147.2 ? 198.9 ? 339.0 ? 0 2 4 6 8 10 12 14 16 18 20 2.2v 2.5v 3.0v 3.5v 4.0v 4.5v 5.0v 5.5v 6.0v mhz 5.1 ? 12.0 ? 19.7 ? 39.4 ? 61.2 ? 81.0 ? 97.5 ? 122.0 ? 147.2 ? 198.9 ? 339.0 ?
mc81f4 104 october 19, 2009 ver. 1.35 33 8. rom option the rom option is a start - condition byte of the chip. the default rom option value is 00 h (lvr en able and external rc is selected ). it can be changed by appropriate writing tools such as pgmplususb, isp , etc. 8.1 r om o ption 7 6 5 4 3 2 1 0 rom option lvren lvrs C C oscs lvren lvr enable/disable bit 0: enable (r03 ) 1: disable (resetb) lvrs lvr level selection bits 00: 2.4v 01: 2.7v 10: 3.0v 11: 4.0v C bit4 C bit3 not used mc81f 4 1 04 oscs oscillator selection bits 000: external rc 001: internal rc; 4mhz 010: internal rc; 2mhz 011: internal rc; 1mhz 100: internal rc; 8mhz 101: not available ( note 4 ) 110: not available ( note 5 ) 111: crystal/ceramic oscillator note : 1. when lvr is enabled, lvr level should be set to appropriate value, not default value. 2. when you select the crystal/ceramic oscillator, r33 and r34 pins are automatically selected for xin and xout mode . 3. when you select the external rc, r34 pin is automatically selected for xin mode . 4. if oscs is set by ? 101 ? , oscillator works as ? internal rc; 4mhz ? mode. 5. if oscs is set by ? 110 ? , o s cillator works as ? internal rc; 2mhz ? mode.
mc81f4 104 34 october 19, 2009 ver. 1.35 8.2 read timing rom option is affected 32 mili - second ( typically ) after vdd cross the por level. more precisely saying, the 32 mili - second is the time for 1/2 counting of 1024 divided bit with 4 mhz internal osc. after the rom option is affected, system clock source is changed based on the rom option. and then, rest 1 /2 counting is continued with changed clock source. so, hole stabilization time is variable depend on the clock source. before read rom option after read rom option osc stabilization time formula 250ns x 128(btcr) x 1024( divider ) period x 128(btcr) x 1024( divider ) before + after int - rc 4mhz 32 ms 32 ms 64 ms int - rc 8mhz 32 ms 16 ms 48 ms x - tal 12 mhz 32 ms 10.7 ms 42.7 ms x - ta l 16 mhz 32 ms 8 ms 40 ms note that rom option is affected in osc stabilization time. so even you change the rom option by isp. it is not affected until system is reset. in other words, you must reset the system after change the rom option. table 8 - 1 examples of osc stabilization time por start volt time rom option read 32 ms por level 32 ms @4mhz osc. stabilization time reset process & main program start vdd rising curve figure 8 - 1 rom option read timing diagram
mc81f4 104 october 19, 2009 ver. 1.35 35 9. memory organization this mcu has separ ate d address spaces for the *p rogram memory * and the *d ata memory * . the program memory is a rom which stores a program code. it is not possible to writ e a data at the p rogram memory while the mcu is running . the data memory is a rem which is used by mcu at running time. 9.1 registers there are few registers which are used for mcu operating. accumulator ( a register ) : accumulator is a 8 - bit general purpose register, which is used for accumulating and some data operation s such as transfer, temporary saving, and conditional j udg ment , etc. and it can be used as a part of 16 - bit register with y register as shown below. x, y registers : in the addressing mode , tho se are used as a index register . it makes it possible to access at xth or yth memory from specific address. it is extremely effective for referencing a subroutine table and a memory table . figure 9 - 1 configuration of registers figure 9 - 2 configuration of ya 16 - bit registers a a c c u m u l a t o r x x r e g i s t e r y y r e g i s t e r s p s t a c k p o i n t e r p c l p r o g r a m c o u n t e r p c h p s w p r o g r a m s t a t u s w o r d a y a y t w o 8 - b i t r e g i s t e r s c a n b e u s e d a s a y a 1 6 - b i t r e g i s t e r
mc81f4 104 36 october 19, 2009 ver. 1.35 these registers also have increment, decrement, comparison and data transfer functions, and they can be used as a simple accumulator . stack pointer : stack pointer is an 8 - bit register which indicates the current ? push ? point in the stack area. it is used to push and pop when interrupts or general function call is occurre d. stack pointer identifies the location in the stack to be accessed (save or restore). generally, sp is automatically updated when a subroutine call is executed or an interrupt is accepted. however, if it is used in exce ss of the stack area permitted by the data memory allocating c onfiguration, the user - processed data may be lost. the stack can be located at any position within 0 0h to 0bf h of the internal data memory. the sp is not initialized by hardware, requiring to wr ite the initial value (the location with which the use of the stack starts) by using the initialization routine. normally, the initial value of b fh is used. figure 9 - 3 stack pointer figure 9 - 4 stack operation s p 0 0 h s t a c k a d d r e s s ( 0 0 h C 0 b f h ) 1 5 8 7 0 h a r d w a r e f i x e d 0 0 h C 0 b f h p c h p c l p s w 0 0 b f 0 0 b e 0 0 b d 0 0 b c p o p u p a t e x e c u t i o n o f r e t i i n s t r u c t i o n 0 0 b c 0 0 b f p c h p c l p s w 0 0 b f 0 0 b e 0 0 b d 0 0 b c p u s h d o w n a t a c c e p t a n c e o f i n t e r r u p t 0 0 b f 0 0 b c p c h p c l 0 0 b f 0 0 b e 0 0 b d 0 0 b c p o p u p a t e x e c u t i o n o f r e t i n s t r u c t i o n 0 0 b d 0 0 b f p c h p c l 0 0 b f 0 0 b e 0 0 b d 0 0 b c p u s h d o w n a t e x e c u t i o n o f a c a l l / t c a l l / p c a l l 0 0 b f 0 0 b d s p b e f o r e x e c u t i o n s p a f t e r e x c c u t i o n a 0 0 b f 0 0 b e 0 0 b d 0 0 b c p o p u p a t e x e c u t i o n o f p o p i n s t r u c t i o n p o p a ( x , y , p s w ) 0 0 b f 0 0 b e a 0 0 b f 0 0 b e 0 0 b d 0 0 b c p u s h d o w n a t e x e c u t i o n o f p u s h i n s t r u c t i o n p u s h a ( x , y , p s w ) 0 0 b f 0 0 b e s p b e f o r e x e c u t i o n s p a f t e r e x c c u t i o n s t a c k d e p t h 0 0 b f 0 1 0 0
mc81f4 104 october 19, 2009 ver. 1.35 37 program status word : program status word (psw)contains several bits that reflect the current state of the cpu. it contains the negative flag, the overflow flag, the break flag the half carry (for bcd operation), the interrupt enable flag, the zero flag, and the carry flag. [carry flag c] this flag stores any carry or borrow from the alu of cpu after an arithm etic operation and is also changed by the shift instruction or rotate instruction. [zero flag z] this flag is set when the result of an arithmetic operation or data transfer is 0 and is cleared by any other result. [interrupt disable flag i] this flag enables/disables all interrupts except interrupt caused by reset or software brk instruction. all interrupts are disabled when cleared to 0. this flag immediately becomes 0 when an interrupt is served. it is set by the ei instruction and cleared by the di instruction. [half carry flag h] after operation, this is set when there is a carry from bit 3 of alu or there is no borrow from bit 4 of alu. this bit can not be set or cleared except clrv instruction with overflow flag (v). [break flag b] this flag is set by software brk instruction to distinguish brk from tcall instruction with the same vector address. [direct page flag g] this flag assigns ram page for direct addressing mode. in the direct addressing mode, addressing area is from zero page 00h to 0ffh when this flag is "0". if it is set to "1", addressing area is assigned 100h to 1ffh. it is set by setg instruction and cleared by clrg. [overflow flag v] this flag is set to 1 when an overflow occurs as the result of an arithmetic operation invol ving signs. an overflow occurs when the result of an addition or subtraction exceeds +127(7fh) or - 128(80h). the clrv instruction clears the overflow flag. there is no set instruction. when the bit instruction is executed, bit 6 of memory is copied to this flag. [negative flag n] figure 9 - 5 psw ( program status word ) registers n m s b l s b n e g a t i v e f l a g v g b h i z c o v e r f l o w f l a g s e l e c t d i r e c t p a g e b r k f l a g c a r r y f l a g r e c e i v e s c a r r y o u t z e r o f l a g i n t e r r u p t e n a b l e f l a g h a l f c a r r y f l a g r e c e i v e s c a r r y o u t f r o m b i t 1 o f a d d i t i o n o p e r a n d s w h e n g = 1 , p a g e i s s e l e c t e d t o p a g e 1
mc81f4 104 38 october 19, 2009 ver. 1.35 this flag is set to match the sign bit (bit 7) status of the result of a data or arithmetic operation. when the bit instruction is executed, bit 7 of memory is copied to this flag.
mc81f4 104 october 19, 2009 ver. 1.35 39 9.2 p rogram m emory a 16 - bit program counter is capable of addressing up to 64k bytes, but this device has 4k bytes program memory space only physically i mplemented. accessing a location above ffffh will cause a wrap - around to 0000h. figure 9 - 6 shows a map of program memory. after reset, the cpu begins execution from reset vector which is stored in address f ffeh and ffffh . as shown in figure 9 - 6 , each area is assigned a fixed location in program memory. program m emory area contains the user program page call (pcall) area contains subroutine program to reduce program byte length by using 2 bytes pcall instead of 3 bytes call instruction. if it is frequently called, it is more useful to save program byte length. table call (tcall) causes the cpu to jump to each tcall address, where it commences the execution of the service routine. th e table call service area spaces 2 - byte for every tcall: 0ffc0h for tcall15, 0ffc2h for tcall14, etc., as shown in figure 9 - 7 . the interrupt causes the cpu to jump to specific location where it commences the execution of the service routine. the interrupt service locations spaces 2 - byte interval . the external interrupt 0 , for example , is assigned to location 0fffc h . any area from 0ff00 h to 0ffff h , if it is not going to be used, its service location is available as general p urpose program memory. example : figure 9 - 6 program memory map p c a l l a r e a t c a l l a r e a i n t e r r u p t v e c t o r a r e a 0 f f f f h 0 f f d f h 0 f f e 0 h 0 f f c 0 h 0 f f 0 0 h 0 f e f f h 4 k r o m 0 f 0 0 0 h
mc81f4 104 40 october 19, 2009 ver. 1.35 figure 9 - 7 pcall and tcall memory area 0 f f c 0 h 0 f f c b h p r o g r a m m e m o r y 0 f f c 1 h t c a l l 1 5 t c a l l 1 4 t c a l l 1 3 t c a l l 1 2 t c a l l 1 1 t c a l l 1 0 t c a l l 9 t c a l l 8 t c a l l 7 t c a l l 6 t c a l l 5 t c a l l 4 t c a l l 3 t c a l l 2 t c a l l 1 t c a l l 0 0 f f c 2 h 0 f f c 3 h 0 f f c 4 h 0 f f c 5 h 0 f f c 6 h 0 f f c 7 h 0 f f c 8 h 0 f f c 9 h 0 f f c a h 0 f f c c h 0 f f c d h 0 f f c e h 0 f f c f h 0 f f d 0 h 0 f f d 1 h 0 f f d 2 h 0 f f d 3 h 0 f f d 4 h 0 f f d 5 h 0 f f d 6 h 0 f f d 7 h 0 f f d 8 h 0 f f d 9 h 0 f f d a h 0 f f d b h 0 f f d c h 0 f f d d h 0 f f d e h 0 f f d f h 0 f f 0 0 h p c a l l a r e a m e m o r y p c a l l a r e a ( 2 5 6 b y t e ) 0 f f f f h
mc81f4 104 october 19, 2009 ver. 1.35 41 example : usage of tcall lda #5 tcall 0fh ;1byte instruction : ;instead of 3 bytes : ;normal call ;table call routine func_a : lda lrg0 ret func_b : lda lrg1 ret ;table call add. area org 0ffc0h ;tcall address area dw func_a dw func_b
mc81f4 104 42 october 19, 2009 ver. 1.35 9.3 d ata memory figure 9 - 8 shows the int ernal data memory space availa ble. data memory is divided into two groups, a user ram / stack memory and c ontrol registers . 9.4 user memory the mc8 1 f 4104 has a 192 bytes user memory (r am) including stack area . so it has only one memory page (page0). 9.5 stack area the stack provides the area where the return address is saved before a jump is performed during the processing routine at the execution of a subroutine call instruction or the acceptance of an interrupt. when returning from the processing routine, executing the subroutine return instruction [ret] restores the contents of the program counter from the stack; executing the interrupt return instruction [reti] restores the contents o f the program counter and flags. the save/restore locations in the stack are determined by the stack pointed (sp). the sp is automatically decreased after the saving, and increased before the restoring. this means the value of the sp indicates the stack l ocation number for the next save. refer to figure 9 - 4 . . 9.6 control registers ( sfr ) the control registers are used by the cpu and peripheral function blocks for control ling the desired operation of the device. therefore these registers contain control and status bits for the interrupt system, the timer/ counters, analog to digital converters and i/o ports. the control registers are in address range of 0c0 h to 0ff h . it also be called by sfr(special function registers). note that unoccupied addresses may not be implemented on the chip. read accesses to these addresses will in general return random data, and write accesses will have an indeterminate effect. more detailed information of each registers are explained in each peripheral section. note : write only registers can not be accessed by bit manipulation instruction. do not use read - modify - write instruction. use byte manipulation instruction, for example ldm . example : to write at ckctlr ldm ckctlr,#0ah ;divide ratio( 32) address register name mnemonic r/w initial value hex 00c0h r0 port data register r0 r/w 0 0 1 0 0 1 0 0 00c6h r0 port control register high byte r0conh r/w 0 0 0 C 0 0 0 1 figure 9 - 8 data memory map 0 3 0 0 h 0 0 0 0 h 0 0 b f h p a g e 0 0 0 f f h u s e r m e m o r y o r s t a c k a r e a ( 1 9 2 b y t e s ) c o n t r o l r e g i s t e r ( 6 4 b y t e s ) 0 0 c 0 h ( w h e n g - f l a g = 0 , t h i s p a g e 0 i s s e l e c t e d
mc81f4 104 october 19, 2009 ver. 1.35 43 00c7h r0 port control register middle byte r0conm r/w 0 0 0 C C C 0 0 00c8h r0 port control register low byte r0conl r/w C C 0 1 0 0 0 0 00c9h r0 port pull - up resistor enable register pur0 r/w 0 0 0 0 C 0 0 0 00cah r0 port external interrupt register eint0 r/w C C 0 0 0 0 0 0 00cch r0 port external interrupt request register erq0 r/w C C C C C 0 0 0 00d0h timer 2 status and control register t2scr r/w C C 0 0 0 0 0 0 00d1h timer 2 data register t2dr r/w 1 1 1 1 1 1 1 1 00d2h timer 2 counter register t2cr r 0 0 0 0 0 0 0 0 00d3h timer 3 status and control register t3scr r/w C C 0 0 0 0 0 0 00d4h timer 3 data register t3dr r/w 1 1 1 1 1 1 1 1 00d5h timer 3 counter register t3cr r 0 0 0 0 0 0 0 0 00ddh a/d mode register admr r/w 0 0 0 0 0 0 0 0 00deh a/d converter data register high byte addrh r x x x x x x x x 00dfh a/d converter data register low byte addrl r x x x x C C C C 00e2h pwm status and control register pwmscr r/w 0 0 C C C C C C 00e3h pwm period and duty register pwmpdr r/w C C C C 1 1 1 1 00e6h pwm2 data register pwm2dr r/w 1 1 1 1 1 1 1 1 00eah interrupt enable register high byte ienh r/w C C C C 0 0 0 0 00ebh interrupt enable register low byte ienl r/w C C C C C 0 C 0 00ech interrupt request register high byte irqh r/w C C C C 0 0 0 0 00edh interrupt request register low byte irql r/w C C C C C 0 C 0 00f1h basic timer counter register btcr r x x x x x x x x 00f2h clock control register ckctlr r/w C C C 1 0 1 1 1 00f3h power on reset control register porc r/w 0 0 0 0 0 0 0 0 00f4h watchdog timer register wdtr r/w 0 1 1 1 1 1 1 1 00f5h stop & sleep mode control register sscr r/w 0 0 0 0 0 0 0 0 00f6h watchdog timer status register wdtsr r/w 0 0 0 0 0 0 0 0 00f7h watchdog timer counter register wdtcr r x x x x x x x x mnemonic address bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 hex r0 00c0h r0 port data register r0conh 00c6h r07 C r06 r05 r0conm 00c7h r04 C C C r03 r0conl 00c8h C C r02 r01 r00 pur0 00c9h pur07 pur06 pur05 pur04 C pur02 pur01 pur00 eint0 00cah C C ext 2ie ext 1ie ext 0ie table 9 - 1 control register 1/2
mc81f4 104 44 october 19, 2009 ver. 1.35 erq0 00cch C C C C C ext 2i r ext 1i r ext 0i r t2scr 00d0h C C t2ms t2cc t2cs t2dr 00d1h timer 2 data register t2cr 00d2h timer 2 counter register t3scr 00d3h C C t3ms t3cc t3cs t3dr 00d4h timer 3 data register t3cr 00d5h timer 3 counter register admr 00ddh ssbit eoc adclk adch addrh 00deh a/d converter data register high byte addrl 00dfh a/d converter data register low byte pwmscr 00e2h pol2 pwms C C C C C C pwmpdr 00e3h C C C C p2dh p2dl pph ppl pwm2dr 00e6h pwm 2 data register ienh 00eah C C C C t2 m ie t2ov ie t3 m i e t3ov ie ienl 00ebh C C C C C wdtie C btie irqh 00ech C C C C t2 m i r t2ovi r t3 m i r t3ovi r irql 00edh C C C C C wdti r C bti r btcr 00f1h basic timer counter register ckctlr 00f2h C C C wdton btcl bts porc 00f3h poren wdtr 00f4h wdtcl wdtcmp sscr 00f5h stop and sleep control register wdtsr 00f6h watchdog timer status register wdtcr 00f7h watchdog timer counter register table 9 - 2 control register 2 /2
mc81f4 104 october 19, 2009 ver. 1.35 45 9.7 addressing modes the mc8 1fxxx series mcu uses six addressing modes; - register addressing - immediate addressing - direct page addressing - absolute addressing - indexed addressing - indirect addressing register addressing register addressing means to access to the data of the a, x, y, c and psw registers . for example ? asl ( a rithmetic shift left ) ? only accesses the a register. immediate addressing in this mode, second byte (operand) is accessed as a data immediately. example : : adc #35h ;op code is 04 h : : when g - flag is 1, then ram address is defined by 16 - bit address which is composed of 8 - bit ram paging register (rpr) and 8 - bit immediate data. example :
mc81f4 104 46 october 19, 2009 ver. 1.35 : ;when g = 1, rpr = 1 ldm #35h,#55h ;op code is 0 e4 h : : direct page addressing - > dp in this mode, a n address is specified within direct page. current accessed page is selected by rpr(ram p a ge select register). and dp( direct page ) is an one byte data which indicates the target address in the current accessed page. example : : ;when g = 0 lda 35h ;a = [35h] : ; op code is 0c5h : absolute addressing absolute addressing sets corresponding memory data to data, i.e. second byte (operand i) of command becomes lower level address and third byte (operand ii) becomes upper level address. with 3 bytes command, it is possible to access to whole memory area. adc, and, cmp, cmpx, cmpy, eor, lda, ldx,ldy, or, sbc, sta, stx, sty the operation within data memory (ram) : asl, bit, dec, inc , lsr, rol, ror example :
mc81f4 104 october 19, 2009 ver. 1.35 47 : ;when g = 0 adc !0f035h ;a = a + c + rom[0f035h] : ; op code is 07h : example : addressing accesses the address 0135 h regardless of g - flag. : ;when g = 0 inc !0135h ;increase rom[135h] : ; op code is 98h : indexed addressing x indexed direct page (no offset) {x} in this mode, a n address is specified by the x register. adc, and, cmp, eor, lda, or, sbc, sta, xma example :
mc81f4 104 48 october 19, 2009 ver. 1.35 : ;when g = 1, x = 15h lda {x} ;a = rom[(rpr<<8) + x] : ;op code is 0d4h : x indexed direct page, auto increment {x}+ in this mode, a address is specified within direct page by the x register and the content of x is i ncreased by 1. lda, sta example: : ;when g = 0, x = 35h lda {x}+ ;a = rom[(rpr<<8) + x] : ; and x = x + 1 : ;op code is 0dbh : x indexed direct page (8 bit offset) dp+x this address value is the second byte (operand) of command plus the data of x - register. and it assigns the memory in d irect p age. adc, and, cmp, eor, lda, ldy, or, sbc, sta,sty, xma, asl, dec, inc, lsr, rol, ror example :
mc81f4 104 october 19, 2009 ver. 1.35 49 : ;when g = 0, x = 0f 5h lda 45h + x ; op code is 0c6h : ; : ; : y indexed direct page (8 bit offset) dp+y this address value is the second byte (operand) of command plus the data of y - register, which assigns memory in direct page. this is same with above ? x indexed direct page ?. use y register instead of x. y indexed absolute !abs+y accessing the value of 16 - bit absolute address plus y - register value . this addressing mode c an specify memory in whole area. example : : ;when y = 55h lda !0fa00h+y ;op code is d5h : indirect addressing direct page indirect [dp] assigns data address to use for accomplishing command which sets memory data (or pair memory) by operand. also index can be used with index register x,y.
mc81f4 104 50 october 19, 2009 ver. 1.35 jmp, call example : : ;when g = 0 jmp [35h] ;op code is 3fh : x indexed indirect [dp+x] processes memory data as data, assigned by 16 - bit pair memory which i s determined by pair data [dp+x+1][dp+x] operand plus x - register data in direct page. adc, and, cmp, eor, lda, or, sbc, sta example :
mc81f4 104 october 19, 2009 ver. 1.35 51 : ;when g = 0 : ; x = 10h adc [25h + x] ;op code is 16h : y indexed indirect [dp]+y processes memory data as data, assigned by the data [dp+1][dp] of 16 - bit pair memory paired by operand in direct page plus y - register data. adc, and, cmp, eor, lda, or, sbc, sta example : : ;when g = 0 : ; y = 10h adc [25h + y] ;op code is 17h : absolute indirect [!abs] the program jumps to address specified by 16 - bit absolute address. jmp
mc81f4 104 52 october 19, 2009 ver. 1.35 example : : ;when g = 0 jmp [0e025h] ;op code is 1fh :
mc81f4 104 october 19, 2009 ver. 1.35 53 10. i/o p orts the mc81f 4 1 04 microcontroller has one i/o port, p0. the cpu accesses ports by writing or reading port register directly. 10.1 r0 port registers r0conh C r05~07 r0 port control high register 00c6h when programming the port, please remember that any alternative peripheral i/o function that def i ned by the r0conh register must also be enabled in the associated peripheral module. 7 6 5 4 3 2 1 0 r0conh r07 - r06 r05 reset value: 000 - _0001b r/w r/w r/w r/w r/w r/w rw r/w r07 r07/an7/vref/ec3/ ext 2 000: schmitt trigger i nput mode (ec3 /ext2 ) 001: output mode, open - drain 010: alternative function (an7) 011: alternative function (vref) 1xx: o utput mode, p ush - pull C bit4 not used for mc81f4104 r06 r06/an6/ec2/ ext 1 00: schmitt trigger i nput mode (ec2 /ext1 ) 01: output mode, open - drain 10: alternative function (an6) 11: o utput mode, p ush - pull r05 r05/an5 00: schmitt trigger i nput mode 01: output mode, open - drain 10: alternative function (an5) 11: o utput mode, p ush - pull
mc81f4 104 54 october 19, 2009 ver. 1.35 r0conm C r03~0 4 r0 port control middle register 00c7h when programming the port, please remember that any alternative peripheral i/o function that def i ned by the r0conm register must also be enabled in the associated peripheral module. 7 6 5 4 3 2 1 0 r0conm r04 - - - r03 reset value: 000 - _ -- 00b r/w r/w r/w r/w r/w r/w r/w r/w r04 r04/an4/ pwm2 o/t2o/ ext 0 000: schmitt trigger i nput mode (ext0) 001: output mode, open - drain 010: alternative function (an4) 011: alternative function ( pwm2 o/t2o) 1xx: o utput mode, p ush - pull C bit4 C r03 r03/resetb ( *note* ) 00: schmitt trigger i nput mode 01: output mode, open - drain 10: not available 11: not available note : if you want to use resetb, the lvren (rom option [7]) must select to lvr disable mode ( ? 1 ? ). if you want to use r35, the lvren (rom option [7]) must select to lvr enable mode (? 0 ? ). even you are in case of using emulator you must select the rom option switch properly to use those r03 ports.
mc81f4 104 october 19, 2009 ver. 1.35 55 r0conl C r00~02 r0 port control low register 00c8h when programming the port, please remember that any alternative peripheral i/o function that def i ned by the r0conl register must also be enabled in the associated peripheral module. 7 6 5 4 3 2 1 0 r0conl C C r02 r01 r00 reset value: -- 01_0000b C C C bit7 C r02 r02/an2 00: schmitt trigger i nput mode 01: output mode, open - drain 10: alternative function (an2) 11: o utput mode, p ush - pull r01 r01/xout/an1 ( *note* ) 00: schmitt trigger i nput mode 01: output mode, open - drain 10: alternative function (an1) 11: o utput mode, p ush - pull r00 r00/xin/an0 ( *note* ) 00: schmitt trigger i nput mode 01: output mode, open - drain 10: alternative function (an0) 11: o utput mode, p ush - pull note : if you want to use x in and x out , the oscs (rom option [2:0]) must select to crystal/ceramic oscillator mode (111b). if you want to use r00 and r01 , the oscs (rom option [2:0]) must select to internal rc mode ( 001b , 010b, 011b, 100b ). even you are in case of using emulator , you must select the osc option as an internal rc mode to use r00 and r01 ports as general i/o ports.
mc81f4 104 56 october 19, 2009 ver. 1.35 pur0 r0 port pull - up enable registe r 00c9h using the pur0 register, you can configure pull - up resistors to individual r 07 - r 00 pins. 7 6 5 4 3 2 1 0 pur0 pur07 pur06 pur05 pur04 - pur02 pur01 pur00 reset value: 00h r/w r/w r/w r/w r/w r/w r/w r/w pur07 r07 pull - up resistor enable bit 0: disable pull - up resistor 1: enable pull - up resistor pur06 r06 pull - up resistor enable bit 0: disable pull - up resistor 1: enable pull - up resistor pur05 r05 pull - up resistor enable bit 0: disable pull - up resistor 1: enable pull - up resistor pur04 r04 pull - up resistor enable bit 0: disable pull - up resistor 1: enable pull - up resistor - bit 3 not used for mc81f4104 pur02 r02 pull - up resistor enable bit 0: disable pull - up resistor 1: enable pull - up resistor pur01 r01 pull - up resistor enable bit 0: disable pull - up resistor 1: enable pull - up resistor pur00 r00 pull - up resistor enable bit 0: disable pull - up resistor 1: enable pull - up resistor r0 r0 port data register 00c0h 7 6 5 4 3 2 1 0 r0 r07 r06 r05 r04 r03 r02 r01 r00 reset value: 00h r/w r/w r/w r/w r/w r/w r/w r/w in input mode, it represents the r0 port status. in output mode, r0 port represents it. 1: high 0 : low
mc81f4 104 october 19, 2009 ver. 1.35 57 11. interrutp c ontroller the mc8 1 f 4 1 04 interrupt circuits consist of interrupt enable register (ienh, ienl), interrupt request flags of irqh, irql, priority circuit, and master enable flag (i flag of psw). and 9 interrupt s ources are provided. the interrupt v ector addresses are shown in ? 11.5 interrupt vector & priority table ? on page 63 . interrupt enable registers are shown in next paragraph . these registers are composed of interrupt enable flags of each interrupt source and these flags determine whether an interrupt will be accepted or not. when the enable flag is 0, a corresponding interrupt source is disabled . note that psw contains also a master enable bit, i - flag, which disables all interrupts at once. figure 11 - 1 block diagram of interrupt w a t c h d o g t i m e r i n t e r r u p t e x t e r n a l i n t e r r u p t 1 e x t e r n a l i n t e r r u p t 0 e x t 0 i r e x t 1 i r e x t e r n a l i n t e r r u p t 2 e x t 2 i r e x t 0 i e i n t e r r u p t r e q u e s t i n t e r r u p t e n a b l e e x t 1 i e e x t 2 i e t i m e r 2 m a t c h i n t e r r u p t t 2 m i r t 2 o v i r t 2 o v i e t 2 m i e t i m e r 2 o v e r f l o w i n t e r r u p t t i m e r 3 m a t c h i n t e r r u p t t 3 m i r t 3 o v i r t 3 o v i e t 3 m i e t i m e r 3 o v e r f l o w i n t e r r u p t w d t i r w d t i e p r i o r i t y c o n t r o l r e l e a s e s t o p / s l e e p i - f l a g i n t e r r u p t m a s t e r e n a b l e f l a g t o c p u i n t e r r u p t v e c t o r a d d r e s s g e n e r a t o r b a s i c t i m e r i n t e r r u p t b t i r b t i e
mc81f4 104 58 october 19, 2009 ver. 1.35 11.1 registers ienh interrupt enable high register 00eah 7 6 5 4 3 2 1 0 ienh - - - - t2 m ie t2ovi e t2 m ie t3ovi e reset value: ---- _0000b r/w r/w r/w r/w r/w r/w r/w r/w C bit7 C bit4 not used for mc81f4104 t2 m ie timer 2 match interrupt enable bit 0: disable interrupt 1: enable interrupt t2ov ie timer 2 overflow interrupt enable bit 0: disable interrupt 1: enable interrupt t3 m ie timer 3 match interrupt enable bit 0: disable interrupt 1: enable interrupt t3ov ie timer 3 overflow interrupt enable bit 0: disable interrupt 1: enable interrupt ienl interrupt enable low register 00ebh 7 6 5 4 3 2 1 0 ienl - - - - - wdtie C bitie reset value: 00h r/w r/w r/w r/w r/w r/w C r/w C bit7 C bit3 not used for mc81f4104 wdtie watchdog timer interrupt enable bit 0: disable interrupt 1: enable interrupt C bit1 not used for mc81f4104 btie basic timer interrupt enable bit 0: disable interrupt 1: enable interrupt
mc81f4 104 october 19, 2009 ver. 1.35 59 irqh interrupt requsest high register 00ech 7 6 5 4 3 2 1 0 iqrh - - - - t2 m i r t2ovi r t3 m i r t3ovi r reset value: ---- _0000b r/w r/w r/w r/w r/w r/w r/w r/w C bit7 C bit4 not used for mc81f4104 t2 m i r timer 2 match interrupt request flag 0: interrupt request flag is not pending, request flag bit clear 1: interrupt request flag is pending t2ovi r timer 2 overflow interrupt request flag 0: interrupt request flag is not pending, request flag bit clear 1: interrupt request flag is pending t3 m i r timer 3 match interrupt request flag 0: interrupt request flag is not pending, request flag bit clear 1: interrupt request flag is pending t3ovi r timer 3 overflow interrupt request flag 0: interrupt request flag is not pending, request flag bit clear 1: interrupt request flag is pending irql interrupt requsest low register 00e d h 7 6 5 4 3 2 1 0 irql - - - - wdti r C biti r reset value: 00h r/w r/w r/w r/w r/w r/w C r/w C bit7 C bit4 not used for mc81f4104 wdti r watchdog timer interrupt request flag 0: interrupt request flag is not pending, request flag bit clear 1: interrupt request flag is pending C bit1 not used for mc81f4104 bti r basic timer interrupt request flag 0: interrupt request flag is not pending, request flag bit clear 1: interrupt request flag is pending
mc81f4 104 60 october 19, 2009 ver. 1.35 11.2 interrupt sequence an interrupt request is held until the interrupt is accepted or the interrupt latch is cleared to 0 by a reset or an instruction. interrupt acceptance sequence requires 8 cycles of fxin ( 1 s at fxin= 4mhz) after the completion of the current instruction execution. the interrupt service task is terminated upon execution o f an interrupt return instruction [reti]. interrupt acceptance 1. the interrupt master enable flag (i - flag) is cleared to 0 to temporarily disable the acceptance of any following ma s kable interrupts. when a non - maskable interrupt is accepted, the acceptance of any following interrupts is temporarily disabled. 2. interrupt request flag for the interrupt source accepted is cleared to 0. 3. the contents of the program counter (return address) and the program status word are saved (pushed) onto the stack area. the stack pointer decreases 3 times. 4. the entry address of the interrupt service program is read from the vector table address and the entry address is loaded to the program counter. 5. the instruction stored at the entry address of the interrupt service program is executed. a interrupt request is not accepted until the i - flag is set to 1 even if a reque sted interrupt has higher priority than that of the current interrupt being serviced. when nested interrupt service is required, the i - flag should be set to 1 by ei instruction in the interrupt service program. in this case, acceptable interrupt sourc es are selectively enabled by the individual interrupt enable flags. saving/restoring general - purpose register the program status word are automatically saved on the stack, but accumulator and other registers are not saved itself. these registers are save d by the software if necessary. also, when multiple interrupt services are nested, it is necessary to avoid using the same data memory area for saving registers. the following method is used to save/restore the general - purpose registers. figure 11 - 2 timing chart of interrupt acceptance and interrupt return instruction
mc81f4 104 october 19, 2009 ver. 1.35 61 example: register save using push and pop instructions . intxx : push a push x push y ;save acc. ;save x reg. ;save y reg. ;; interrupt processing ;; pop y pop x pop a reti ;restore y reg. ;restore x reg. ;restore acc. ;return general - purpose register save/restore using push and pop instructions; figure 11 - 3 saving/restoring in interrupt routine
mc81f4 104 62 october 19, 2009 ver. 1.35 11.3 brk interrupt software interrupt can be invoked by brk instruction, which has the lowest priority order. interrupt vector address of brk is shared with the vector of tcall 0 (refer to program memory section). when brk interrupt is generated, b - flag of psw is set to distinguish brk from tcall 0. each processing step is determined by b - flag as shown in f igure 11.4 multi interrupt if two requests of different priority levels are received simultaneously, the request of higher priority level is serviced. if requests of the interrupt are received at the same time simultaneously, an internal p olling sequence determines by hardware which request is serviced. however, multiple processing through software for special features is possible. generally when an interrupt is accepted, the i - flag is cleared to disable any further interrupt. but as user s ets i - flag in interrupt routine, some further interrupt can be serviced even if certain interrupt is in progress. in this example, the ext 1 interrupt can be serviced without any pending, even timer1 is in progress. because of re - setting the interrupt enable registers ienh,ienl and master enable ei in figure 11 - 4 execution of multi interrupt
mc81f4 104 october 19, 2009 ver. 1.35 63 11.5 interrupt vector & priority table address interrupt int number priority 0ffe0h basic interval timer int0 15 ( lowest priority) 0ffe2h watchdog timer int1 14 0ffe4h timer 3 overflow int2 13 0ffe6h timer 3 match int3 12 0ffe8h timer 2 overflow int4 11 0ffeah timer 2 match int5 10 0ffech - - 9 0ffeeh - - 8 0fff0h - - 7 0fff2h - - 6 0fff4h - - 5 0fff6h - - 4 0fff8h external 2 int12 3 0fffah external 1 int13 2 0fffch external 0 int14 1 0fffeh reset int15 0 ( highest priority) table 11 - 1 interrupt vector & priority
mc81f4 104 64 october 19, 2009 ver. 1.35 12. external i nterrupts the external interrupt pins are edge triggered depending on the ? external interrupt register s ? . the edge detection of external interrupt has three transition activated mode: rising edge, falling edge, and both edge. 12.1 register s eint0 C ext 2~ 0 / r04~r07 r0 port external interrupt enable high register 00cah you can use eint0h register setting to select disable interrupt or e nable i nterrupt ( by falling, rising, or both falling and rising edge). 7 6 5 4 3 2 1 0 eint0 - ext 2ie ext 1ie ext 0ie reset value: -- 00_0000b r/w r/w r/w r/w r/w r/w r/w r/w - bit 7 C ext 2ie r07/ ext 2 external interrupt enable bits 00: disable interrupt 01: enable interrupt by falling edge 10: enable interrupt by rising edge 11: enable interrupt by both falling and rising edge ext 1ie r06/ ext 1 external interrupt enable bits ext 0ie r04/ ext 0 external interrupt enable bits erq0 C ext 10,11,0~5 / r00~r07 r0 port external interrupt request register 00cch when an interrupt is generated, the bit of e rq 0 that generated it is cleared by the hardware when the service routine is vectored to only if the interrupt was transition - activated. 7 6 5 4 3 2 1 0 erq0 - - - - - ext 2i r ext 1i r ext 0i r reset value: 00h r/w r/w r/w r/w r/w r/w r/w r/w - bit 7 C ext 2i r r07/ ext 2 external interrupt request flag 0: interrupt request flag is not pending, request flag bit clear 1: interrupt request flag is pending ext 1i r r06/ ext 1 external interrupt request flag ext 0i r r04/ ext 0 external interrupt request flag
mc81f4 104 october 19, 2009 ver. 1.35 65 12.2 procedure to generate external interrupt, following steps are required, 1. prepare external interrupt sub - routine (function) . 2. s et external interrupt pins to input mode . (use rnconh/m/l registers). 3. enable the external interrupt and select the edge mode. (use eint0 register). 4. make sure global interrupt is enabled . (use ? ei ? instruction). a fter finish above steps , the external interrupt sub - routine is calling, when the edge is detected. when the generated external interrupt is one of the external interrupt group s , the eintf register is used to recognize which external interrupt is generated.
mc81f4 104 66 october 19, 2009 ver. 1.35 13. o scillation c ircuits there are few example circuits for main oscillators. oscillation circuit is designed to be used either with a ceramic resonator or crystal oscillator. since each crystal and ceramic resonator have their own characteristics, the user should consult the crystal manufacturer for appropriate values of external components. 13.1 main oscillation circuit s c1, c2 = 10 ~ 30 pf * the example load capacitor value(c1, c2) is common value but may not be appropriate for some crystal or ceramic resonator. xout pin can be used as a normal pin. figure 13 - 1 crystal/ceramic oscillator figure 13 - 2 external clock figure 13 - 3 external rc oscillator c1 c2 x in x out x in x out
mc81f4 104 october 19, 2009 ver. 1.35 67 xout and xin pins can be used as normal pins 13.2 pcb layout for reference, here is a n example layout for oscillator circuit. note : minimize the wiring length. do not allow the wiring to intersect with other signal conductors. do not allow the wiring to come near changing high current. set the potential of the grounding position of the oscillator capacitor to that of v ss . do not ground it to any ground pattern where high current is present. do not fetch signals from the oscillator. figure 13 - 4 internal rc oscillator figure 13 - 5 layout of oscillator pcb circuit
mc81f4 104 68 october 19, 2009 ver. 1.35 14. b asic i nterval t imer the mc8 1f4 1 04 has one 8 - bit basic interval timer that is free - run and can not be stop ped except when peripheral clock is sto pped . t he basic interval timer generates the time base for watchdog timer counting. it also provides a basic interval timer interrupt . the 8 - bit basic interval timer register (bt c r) is increased every internal count pulse which is divided by prescaler. si nce prescaler has divided ratio by 8 to 1024, the count rate is 1/8 to 1/1024 of the oscillator frequency. as the count overflow from ffh to 00h, this overflow causes the interrupt to be generated. the basic interval timer is controlled by the clock contr ol register (ckctlr). when wri te "1" to bit btcl of ckctlr, b t c r register is cleared to "0" and restart to count - up. the bit btcl becomes "0" after one machine cycle by hardware. the bit wdton decides watchdog timer or the normal 7 - bit timer. source clock can be selected by lower 3 bits of ckctlr.
mc81f4 104 october 19, 2009 ver. 1.35 69 14.1 registers ckctlr clock control reg ister 00f2h 7 6 5 4 3 2 1 0 ckctlr C C C wdton btcl bts reset value: 17h C C C r/w r/w r/w r/w r/w C bit7 C bit5 not used for mc81f 4 1 04 wdton watchdog timer enable bit 0: operate as 7 - bit timer 1: enable watchdog timer btcl basic timer clear bit 0: normal operation (free - run) 1: clear 8 - bit counter (bitr) to 0 , this bit becomes 0 automatically after one machine cycle, and starts counting. bts basic interval timer source clock selection bits 000: fxin/8 001: fxin/16 010: fxin/32 011: fxin/64 100: fxin/128 101: fxin/256 110: fxin/512 111: fxin/1024 ckctlr[2:0] source clock interrupt(overflow) period (ms) @ fxin = 8mhz 000 fxin/8 0.256 001 fxin/16 0.512 010 fxin/32 1.024 011 fxin/64 2.048 100 fxin/128 4.096 101 fxin/256 8.192 110 fxin/512 16.384 111 fxin/1024 32.768 btcr basic timer counter reg ister 00f1h 7 6 5 4 3 2 1 0 btcr o ne byte register reset value: xxh r r r r r r r r a 8 bit count register for the basic interval timer. figure 14 - 1 basic interval timer interrupt period
mc81f4 104 70 october 19, 2009 ver. 1.35 15. watch d og t imer the watchdog timer rapidly detects the cpu malfunction such as endless looping caused by noise or the like, and resumes the cpu to the normal state. the watchdog timer signal for detecting m alfunction can be selected eit her a reset cpu or a interrupt request. when the watchdog timer is not being used for malfunction detection, it can be used as a timer to generate an interrupt at fixed intervals. the watchdog timer use s the b asic i nterval t imer as a clock source. the wa tchdog timer consists of 7 - bit binary counter and the watchdog timer data register. when the value of 7 - bit binary counter is equal to the lower 7 bits of wdtr, the interrupt request flag is generated. this can be used as watchdog timer interrupt or reset the cpu in accordance with the bit wdton. watchdog reset feature is disabled when the watchdog timer status register(wdtsr) value is ? 0a5h ? . note that, wdtsr ? s reset value is ? 00h ? . and reset value of wdton is ? 1 ? . so watchdog timer reset is enabled at re set time. figure 15 - 1 block diagram of basic interval timer/watchdog timer m u x f x x / 1 0 2 4 f x x / 5 1 2 f x x / 2 5 6 f x x / 1 2 8 f x x / 6 4 f x x / 3 2 f x x / 1 6 f x x / 8 p r e s c a l e r f x x s t a r t t h e c p u 8 - b i t u p c o u n t e r b i t r b t c l c l e a r b t i r b t i e b t i n t b c k [ 2 : 0 ] w a t c h d o g c o u n t e r ( 7 - b i t ) 7 - b i t c o m p a r a t o r 7 - b i t c o m p a r e d a t a w d t r w d t c l c l e a r c l e a r w t i r w d t i e w d t i n t o v e r f l o w w d t s r t o r e s e t c p u w d t o n o v e r f l o w b a s i c i n t e r v a l t i m e r i n t r e q u e s t b a s i c i n t e r v a l t i m e r i n t e n a b l e w a t c h d o g t i m e r i n t r e q u e s t w a t c h d o g t i m e r i n t e n a b l e
mc81f4 104 october 19, 2009 ver. 1.35 71 15.1 registers wdtr watchdog timer reg ister 00f4h 7 6 5 4 3 2 1 0 wdtr wdtcl wdtcmp reset value: 7fh r/w r/w r/w r/w r/w r/w r/w r/w wdtcl watchdog timer clear bit 0: free - run count 1: when the wdtcl is set to 1 , binary counter is cleared to 0 . and the wdtcl becomes 0 automatically after one machine cycle. counter count up again. wdtcmp bit6 C bit0 7 - bit compare data wdtsr watchdog timer status reg ister 00f6h 7 6 5 4 3 2 1 0 wdtsr o ne byte register reset value: 00h r/w r/w r/w r/w r/w r/w r/w r/w watchdog timer function disable code (for system reset) 10100101: disable watchdog timer function others: enable watchdog timer function figure 15 - 2 watchdog timer timing
mc81f4 104 72 october 19, 2009 ver. 1.35 16. timer 2 the 8 - bit timer 2 is an 8 - bit general - purpose timer. timer 2 ha ve two operating modes, you can select one of them using the a ppropriate t 2 scr setting : - interval timer mode (toggle output at t 2 o pin) - capture input mode with a rising or falling edge trigger at ext 0 pin 16.1 registers t2dr timer 2 data register 00 d1 h 7 6 5 4 3 2 1 0 t2dr o ne byte register reset value: ffh r/w r/w r/w r/w r/w r/w r/w r/w a 8 - bit compare value register for the timer 2 match interrupt. t2cr timer 2 counter register 00 d2 h 7 6 5 4 3 2 1 0 t2cr o ne byte register reset value: 00h r r r r r r r r a 8 - bit count register for the timer 2
mc81f4 104 october 19, 2009 ver. 1.35 73 t2scr timer 2 status and control register ( t2scr ) 00 d0 h to enable the timer 2 match interrupt, you must set 1 to t2 m ie. when the timer 2 match interrupt sub - routine is serviced, the timer 1 match inter rupt request flag bit, t 2 mir , is cleared automatically . to enable the timer 2 overflow interrupt, you must set 1 to t2ov i e. when the timer 2 overflow interrupt sub - routine is serviced, the timer 2 over flow interrupt request flag bit, t2ovir is cleared automatically. 7 6 5 4 3 2 1 0 t2scr - C t2ms t2cc t2cs reset value: -- 00_0000b - C C bit7 - bit6 not used for mc81 f4 1 04 t2ms timer 2 mode selection bit 0: interval mode (t2o) 1: capture mode (ovf can occur) t2cc timer 2 counter clear bit 0: no effect 1: clear the timer 2 counter (when write, automatically cleared t2cs timer 2 clock selection bits 0000: counter stop 0001: not available 0010: not available 0011: not available 0100: not available 0101: external clock (ec2) rising edge 0110: external clock (ec2) falling edge 0111: not available 1000: fxx/1 1001: fxx/2 1010: fxx/4 1011: fxx/8 1100: fxx/16 1101: fxx/64 1110: fxx/256 1111: fxx/1024 note : you must set the t2cc(t2scr.4) bit after set t2dr register. the timer 2 counter value is compared with timer 2 buffer register instead of t2dr. and t2dr value is copied to timer 2 buffer .
mc81f4 104 74 october 19, 2009 ver. 1.35 16.2 timer 2 8 - bit mode timer 2 has the following functional components: - clock frequency divider (fxx divided by 10 24 , 256 , 64 , 1 6 , 8 , 4 , 2 , 1 , fxt) with multiplexer - external clock input pin , ec 2 ( r0 6 ) - i/o pins for capture input , ext 0 (r0 4 ) or match output t 2 o ( r0 4 ) - 8 - bit counter (t 2 c r) , 8 - bit comparator, and 8 - bit reference data register (t 2 d r ) - timer 2 status and control register ( t 2 scr) - timer 2 over flow interrupt and match interrupt generation figure 16 - 1 8 - bit timer 2 block diagram t 2 o t 2 c s t 2 m i r m u x e i n t 0 e x t 0 t i m e r 2 b u f f e r r e g i s t e r t i m e r 2 d a t a r e g i s t e r 8 - b i t u p c o u n t e r ( r e a d - o n l y ) r 8 d a t a b u s 8 t 2 c c t 2 o v i r t 2 o v i e o v f m a t c h m u x f x x / 6 4 e c 2 t 2 o v e r f l o w i n t e r r u p t f x x / 1 6 f x x / 8 f x x / 4 f x x / 2 f x x / 1 c o u n t e r s t o p 8 - b i t c o m p a r a t o r t 2 m i e t 2 m a t c h i n t e r r u p t d a t a b u s c l e a r m a t c h s i g n a l f x x / 2 5 6 c l e a r e x t 0 i n t e r r u p t f x x / 1 0 2 4 t i m e r 2 o v e r f l o w i n t e n a b l e t i m e r 2 o v e r f l o w i n t r e q u e s t t i m e r 2 m a t c h i n t e n a b l e t i m e r 2 m a t c h i n t r e q u e s t t 2 c r t 2 d r t 2 c c m a t c h s i g n a l o v e r f l o w s i g n a l
mc81f4 104 october 19, 2009 ver. 1.35 75 function description interval timer mode a match signal is generated and t 2 o pins are toggled when the t2cr register value equals the t 2 d r register value . the match signal generates a timer match interrupt and clears the t2cr register . capture mode in capture mode, you have to set ext 0 interrupt. when the ext 0 interrupt is occurred, the t2cr register value is loaded into the t2dr register and the t2cr re gister is cleared. and the timer 2 overflow interrupt is generated whenever the t2cr value is overflow ed. so, if you count how many overflow is occurred and read the t2dr value in ext 0 interrupt routine, it is possible to measure the time between two ext 0 interrupts. or it is possible to measure the time from the t2 initial time to the ext 0 interrupt occurred time. the time = ( 256 * tclk ) * overflow_count + (tclk * t2dr) note ? t clk ? is the period time of the timer - counter ? s clock source you must set the t2dr value before set the t2scr register. b ecause t2dr value is fetched when the count is started(the t2cc bit is set) or match/overflow event is occurred .
mc81f4 104 76 october 19, 2009 ver. 1.35 17. timer 3 the 8 - bit timer 3 is an 8 - bit general - purpose timer. timer 3 ha ve two op erating modes, you can select one of them using the appropriate t 3 scr setting : - interval timer mode (toggle output at t 3 o pin) - capture input mode with a rising or falling edge trigger at ext 2 pin 17.1 registers t3dr timer 3 data register 00 d 4 h 7 6 5 4 3 2 1 0 t 3 dr o ne byte register reset value: ffh r/w r/w r/w r/w r/w r/w r/w r/w a 8 - bit compare value register for the timer 3 match interrupt. t3cr timer 3 counter register 00 d 5 h 7 6 5 4 3 2 1 0 t 3 cr o ne byte register reset value: 00h r r r r r r r r a 8 - bit count register for the timer 3
mc81f4 104 october 19, 2009 ver. 1.35 77 t 3 scr timer 3 status and control register 00 d3 h to enable the timer 3 match interrupt, you must set 1 to t3 m ie. when the timer 3 match interrupt sub - routine is serviced, the timer 1 match interrupt request flag bit, t 3 mir , is cleared automatically . to enable the timer 3 overflow interrupt, you must set 1 to t3ovi e. when the timer 3 overflow interrupt sub - routine is serviced, the timer 3 overflow interrupt request flag bit, t 3ovi r , is cleared automatically . 7 6 5 4 3 2 1 0 t3scr C C t3ms t3cc t3cs reset value: 00h C C C bit7 C t3ms timer 3 mode selection bit 0: interval mode 1: capture mode (ovf can occur) t3cc timer 3 counter clear bit 0: no effect 1: clear the timer 3 counter (when write, automatically cleared t3cs timer 3 clock selection bits 0000: counter stop 0001: not available 0010: not available 0011: not available 0100: not available 0101: external clock (ec3) rising edge 0110: external clock (ec3) falling edge 0111: not available 1000: fxx/2 1001: fxx/4 1010: fxx/8 1011: fxx/16 1100: fxx/32 1101: fxx/128 1110: fxx/512 1111: fxx/2048 note : you must set the t3cc(t3scr.4) bit after set t3dr register. the timer 3 counter value is compared with timer 3 buffer register instead of t3dr. and t3dr value is copied to timer 3 buffer .
mc81f4 104 78 october 19, 2009 ver. 1.35 17.2 timer 3 8 - bit mode timer 3 has the following functional components: - clock frequency divider (fxx divided by 2048 , 512 , 128 , 32 , 16 , 8 , 4 , 2 ) with multiplexer - external clock input pin , ec 3 ( r0 7 ) - i/o pins for capture input , ext 2 (r0 7 ) - 8 - bit counter (t 3 c r) , 8 - bit comparator, and 8 - bit reference data register (t 3 d r ) - timer 3 st atus and control register ( t 3 scr) - timer 3 overflow interrupt and match interrupt generation figure 17 - 1 8 - bit timer 3 block diagram t 3 c s t 3 m i r m u x e i n t 0 e x t 2 t i m e r 3 b u f f e r r e g i s t e r t i m e r 3 d a t a r e g i s t e r 8 - b i t u p c o u n t e r ( r e a d - o n l y ) r 8 d a t a b u s 8 t 3 c c t 3 o v i r t 3 o v i e o v f m a t c h m u x f x x / 1 2 8 e c 3 t 3 o v e r f l o w i n t e r r u p t f x x / 3 2 f x x / 1 6 f x x / 8 f x x / 4 f x x / 2 c o u n t e r s t o p 8 - b i t c o m p a r a t o r t 3 m i e t 3 m a t c h i n t e r r u p t d a t a b u s c l e a r m a t c h s i g n a l f x x / 5 1 2 c l e a r e x t 2 i n t e r r u p t f x x / 2 0 4 8 t i m e r 3 o v e r f l o w i n t e n a b l e t i m e r 3 o v e r f l o w i n t r e q u e s t t i m e r 3 m a t c h i n t e n a b l e t i m e r 3 m a t c h i n t r e q u e s t t 3 c r t 3 d r t 3 c c m a t c h s i g n a l o v e r f l o w s i g n a l
mc81f4 104 october 19, 2009 ver. 1.35 79 function description interval timer mode a match signal is generated and t 3 o pins are toggled when the t 3 cr register value equals the t 3 d r register value . the match signal generates a timer match interrupt and clears the t 3 cr register . capture mode in capture mode, you have to set ext 2 interrupt. when the ext 2 interrupt is occurred, the t 3 cr register value is loaded into the t 3 dr register and the t 3 cr register is cleared. and the timer 3 overflow interrupt is generated whenever the t 3 cr value is overflow ed. so, if you count how many overflow is occurred and read the t 3 dr value in ext 2 interrupt routine, it is possible to measure the time between two ext 2 interrupts. or it is possible to measure the time from the t 3 initial time to the ext 2 interrupt occurred time. the time = ( 256 * tclk ) * overflow_count + (tclk * t 3 dr) note ? t clk ? is the period time of the timer - counter ? s clock source you must set the t3dr value before set the t3scr register. b ecause t3dr value is fetched when the count is started(the t3cc bit is set) or match/overflow event is occurred .
mc81f4 104 80 october 19, 2009 ver. 1.35 18. high speed pwm the mc8 1f 4 1 04 ha s one high speed pwm (pulse width modulation) function which shared with timer 2 . in pwm mode, the r 04 /pwm 2o pin operate s as a 10 - bit resolution pwm output port. for this mode, the r04 of r0 con m should be set to alternative function mode . the period of the pwm output is determined by the t2dr (t 2 data register) and pwmpdr [ 1 : 0 ] ( pwm period duty register) and the duty of the pwm output is determined by the p wm2 dr(pwm 2 d ata register) and pwmpdr [ 3 : 2 ] (pwm period duty register ). user can use pwm data by writing the lower 8 - bit period value to the t 2dr and the higher 2 - bit period value to the pw mpd r[ 1 : 0 ]. and the duty value can be used with the pwm2 dr a nd the pwmpdr [ 3 : 2 ] in the same way. the bit pol 2 of pwmscr decides the polarity of duty cycle. the duty value can be changed when the pwm outputs. however the changed duty value is output after the current period is over. and it can be maintained the duty value at present output when changed only period value shown as example of pwm2 . as it were, the absolute duty time is not changed in varying frequency. figure 18 - 1 high speed pwm block diagram m a t c h 8 - b i t c o m p a r a t o r t i m e r 2 b u f f e r r e g i s t e r t i m e r 2 d a t a r e g i s t e r 2 - b i t 2 - b i t 8 - b i t u p c o u n t e r ( r e a d - o n l y ) r 2 - b i t 2 - b i t 8 - b i t c o m p a r a t o r 2 - b i t m u x f x x / 6 4 e c 2 f x x / 1 6 f x x / 8 f x x / 4 f x x / 2 f x x / 1 c o u n t e r s t o p p w m 2 d a t a r e g i s t e r 2 - b i t p w m 2 b u f f e r r e g i s t e r 2 - b i t t 2 c s p w m 2 o t 2 m i r t 2 m i e t 2 m a t c h i n t e r r u p t t 2 c c c l e a r m a t c h s i g n a l s r q p o l 2 m u x c o u n t e r s t o p n o t e : 1 . w h e n y o u c l e a r e d t h e p o l 2 a n d c o u n t e r s t o p , p w m 2 o i s h i g h s t a t u s . 2 . w h e n y o u s e t t h e p o l 2 a n d c o u n t e r s t o p , p w m 2 o i s l o w s t a t u s . f x x / 2 5 6 f x x / 1 0 2 4 t i m e r 2 m a t c h i n t e n a b l e t i m e r 2 m a t c h i n t r e q u e s t t 2 c r t 2 d r p p h , p p l p 2 d h , p 2 d l t 2 c c m a t c h s i g n a l o v e r f l o w s i g n a l
mc81f4 104 october 19, 2009 ver. 1.35 81 note : when user need to change mode from the timer 2 mode to the pwm mode, the timer 2 should be stopped firstly, and then set period and duty register value. if user writes register values and changes mode to pwm mode while timer 2 is in operation, the pwm data would be different from expected data in the beginning. pwm period = [pw mpd r [1 : 0 ]t 2d r+1] x source clock pwm 2 duty = [pw mpd r[ 3 : 2 ]p wm2 dr+1] x source clock if it needed more higher frequency of pwm, it should be reduced resolution. note : if the duty value and the period value are same, the pwm output is determined by the bit pol (1: high, 0: low). and if the duty value is set to 00h, the pwm output is determined by the bit pol(1: low, 0: high). the period value must be same or more than the duty value, and 00 h cannot be used as the period value. figure 18 - 2 example of pwm2 at 8mhz s o u r c e c l o c k p w m p e r i o d , t 2 d r 0 0 0 1 0 2 0 3 0 4 0 5 0 6 0 7 0 9 0 a 0 b 0 c 0 d 0 e 0 f 1 0 8 0 8 1 8 2 8 3 8 4 3 f c 3 f d 3 f e 3 f f 0 0 0 1 0 2 0 3 0 4 0 8 ~ ~ ~ ~ ~ ~ ~ ~ ~ ~ ~ ~ ~ ~ ~ ~ ~ ~ ~ ~ p w m 2 o , p o l 2 = 1 p w m 2 o , p o l 2 = 0 d u t y c y c l e [ ( 1 + 0 c h ) x 2 5 6 u s = 3 . 3 3 m s t 2 s c r = 1 f h t 2 d r = 0 f f h p w m s c r = 3 0 h p w m p d r = 0 3 h p w m 2 d r = 0 c h p e r i o d c y c l e [ ( 1 + 3 f f h ) x 2 5 6 u s = 2 6 2 m s
mc81f4 104 82 october 19, 2009 ver. 1.35 18.1 registers pwmscr pwm status and control register (pwmscr) 00 e 2 h 7 6 5 4 3 2 1 0 pwmscr pol2 pwms - - C C C C reset value: 00 -- _ ---- b r/w r/w r/w r/w C C C C pol2 pwm 2 polarity selection bit 0: pwm 2 duty active low 1: pwm 2 duty active high pwms pwm selection bit 0: timer 2 mode (interval or capture) 1: pwm mode (pwm2o, pwm3o, pwm4o ) C bit5 C bit0 not used for mc81f4104 pwm pdr pwm period duty register 00 e3 h 7 6 5 4 3 2 1 0 pwmpdr - - p2dh p2dl pph ppl reset value: - 0h r/w r/w r/w r/w r/w r/w r/w r/w - bit 7 C p2dh pwm 2 duty high bit pwm2 duty value ( 9,8th bits ) p2dl pwm 2 duty low bit pph pwm period high bit period value ( 9/8th bits ) ppl pwm period low bit pwm2dr pwm 2 data register 00 e6 h 7 6 5 4 3 2 1 0 pwm2dr o ne byte register reset value: ffh r/w r/w r/w r/w r/w r/w r/w r/w a 8 - bit data register for lower bits of 10 - bit pwm 2 duty value.
mc81f4 104 october 19, 2009 ver. 1.35 83 19. 12 - bit adc the 12 - bit a/d converter (adc) module uses successive approximation logic to convert analog levels entering at one of the 1` input channels to equivalent 12 - bit digital values. the analog input level must lie between the v ref and v ss values. the a/d converter has the analog comparator with successive approximation logic, d/a converter logic (resistor string type), a/d mode regi ster (admr), 8 multiplexed analog data input pins (ad0 - ad 2 , ad4 - ad7 ,bgr ), and 12 - bit a/d conversion data output register (addrh/addrl). figure 19 - 1 a/d converter block diagram c l o c k s e l e c t o r a d d r h ( r ) , a d d r l ( r ) - + e o c f l a g c o n t r o l l o g i c c o m p a r a t o r a d c h ( s e l e c t o n e i n p u t p i n o f t h e a s s i g n e d p i n s ) a d c l k i n p u t p i n s m u x r e f e r e n c e v o l t a g e v r e f a v s s a n 1 a n 2 a n 6 a n 7 b g r a n 0 a n 4 a n 5
mc81f4 104 84 october 19, 2009 ver. 1.35 19.1 registers admr a/d mode register 00d dh 7 6 5 4 3 2 1 0 admr ssbit eoc adclk adch reset value: 00h r/w r r/w r/w r/w r/w r/w r/w after reset, the start/stop bit is turned off. you can select only one analog input channel at a time. other analog input ( ad0 - ad 2, ad4 - ad7 ,bgr ) can be selected dynamically by manipulating the adch (admr[4:0]) . and the pins not used for analog input can be used for normal i/o function. ssbit start or stop bit 0: stop operation 1: start operation eoc end of conversion 0: conversion not complete 1: conversion complete adclk a/d clock selection 00: fxx/1 01: fxx/2 10: fxx/4 11: fxx/8 adch a/d input pin selection 0000: an0 0001: an1 0010: an2 0011: not available 0100: an4 0101: an5 0110: an6 0111: an7 1000: available 1001: not available 1010: not available 1011: not available 1100: not available 1101: not available 1110: an14 1111: bgr a ddrh a/d converter data high register 00 de h 7 6 5 4 3 2 1 0 addrh .11 .10 .9 .8 .7 .6 .5 .4 reset value: xxh r r r r r r r r a 8 - bit data register for higher 8 - bits of the 12 - bit adc result . addrl a/d converter data low register 00d fh 7 6 5 4 3 2 1 0 addrl .3 .2 .1 .0 - - - - reset value: x - h r r r r r r r r a 8 - bit data register for lower 4 - bits of the 12 - bit adc result.
mc81f4 104 october 19, 2009 ver. 1.35 85 19.2 procedure to do the a/d converting , follow these basic steps: 1. s et the adc pins as the alternative mode. 2. s e t the admr register for - setting adc channel - setting clock - clearing the ? end of conversion ? bit - starting adc 3. w ait until adc is finished ( check the ? end of conversion ? bit ) when adc is finished, eoc bit is set and ssbit is cleared automatically. 4. read the adcrh and adcrl register to initiate an analog - to - digital conversion procedure, at first you must set adc pin s to alternative function ( ad c analog input ) mode . and you write the channel selection data in the a/d mode register ( a dmr) to select one of analog input channels and set the conversion start / stop bit, ssbit . the pins not used for adc can be used for norma l i/o. to start the a/d conversion, you should set the start / stop bit, ssbit . when a conversion is completed, the end - of - conversion bit , eoc is automatically set to 1 and the result is dumped into the ad dr h/ad dr l register. t hen t he a/d converter enters an idle state. the eoc bit is cleared when ssbit is set. note that, adc interrupt is not provided. note : because the a/d converter has no sample - and - hold circuitry, it is very important that fluctuation of the analog level at the ad0 - ad2,ad4 - ad7 input pins during a conversion procedure be kept to an absolute minimum. any change in the input level, perhaps due to noise, will invalidate the result. if the chip enters to stop or idle mode in conversion process, there will be a leakage current path i n a/d block. you must use stop or idle mode after adc operation is finished. 19.3 c onversion timing the a/d conversion process requires 4 steps (4 clock edges) to convert each bit and 10 clocks to set - up a/d conversion. therefore, total of 66 clocks are requ ired to complete a 12 - bit conversion: when fxx/8 is selected for conversion clock with a 12 mhz fxx clock frequency, one clock cycle is 0.66 ? ? ? ? ? note : the a/d converter needs at least 25 ? ?
mc81f4 104 86 october 19, 2009 ver. 1.35 19.4 i nternal r eference v oltage l evels in the adc function block, the analog input voltage level is compared to the reference voltage. the analog input level must be remain ed within the range v ss to v ref . different reference voltage levels are generated internally along the resistor tree during the analog conversion process for each conversion step. the reference voltage level for the first conversion bit is always 1/2 v ref . 19.5 recommended circuit note : lay out the gnd of v ain as close as possible to the power source. figure 19 - 2 recommended a/d converter circuit v s s m c u a d c i n p u t p o r t a n a l o g i n p u t 1 0 ? f 1 0 4 c 1 0 4 c + - v d d v r e f v d d v a i n ( * n o t e 1 ) 1 0 4 c
mc81f4 104 october 19, 2009 ver. 1.35 87 20. reset 20.1 reset process when the reset even t is occurred , there is a ? stabilization time ? at the beginning. this time is counted from 00h to ffh by bit. so it takes 1/(fxin/ 1 0 24 ) * 256 second. after that, the ? reset process step ? is started. it takes 6 system clock time. a t this time, following status es a re initialized. on - chip hardware initial value p r ogram counter ( pc ) high byte = a byte at ffffh low byte = a byte at f ffeh ffffh and fffeh stores the reset vector. ram page register ( prp ) 0 g - flag ( g ) 0 operation mode oscs setting of rom option control registers initialized by reset values (see ? ? figure 20 - 1 timing diagram after reset table 20 - 1 initializing status by reset 1 2 3 4 5 6 7 f f f e f f f f s t a r t f e a d l o p a d h o s c i l l a t o r r e s e t b a d d r e s s b u s d a t a b u s ? s t a b i l i z a t i o n t i m e t s t = f x i n / 1 0 2 4 1 x 2 5 6 r e s e t p r o c e s s s t e p m a i n p r o g r a m
mc81f4 104 88 october 19, 2009 ver. 1.35 20.2 reset sources there are four reset sources in mc81 f 4104 . those are external reset, watch dog timer reset, power on reset and low voltage reset. 20.3 external reset when the external reset is enabled and the input signal of reset pin is going to low for a while and going to high, the external reset is occurred .( see ? 7.6 serial electric characteristics ? on page 23 for more timing information .) it is possible to use a external power on reset circuit like figur e 20 - 3 . 20.4 watch dog timer reset see ? 15 . watch d og t imer ? on page 70 . figure 20 - 2 reset sources diagram figur e 20 - 3 external power on reset example n o i s e c a n c e l l e r e x t e r n a l r e s e t n o i s e c a n c e l l e r p o r / l v r w d t r e s e t p o w e r o n r e s e t o r l o w v o l t a g e r e s e t b i t c l e a r o v e r f l o w s r q i n t e r n a l r e s e t
mc81f4 104 october 19, 2009 ver. 1.35 89 20.5 power on reset there is a internal power on reset circuit internally. we simply call it por. por o c curs the reset event w hen vdd is rising over the por level. note that, por can be enabled and disabled by the porc register. and default setting is ? por enable ? . so at the first time power is supplied, por is working always even external reset is enabled. porc power on reset control register (00f3h) 7 6 5 4 3 2 1 0 porc o ne byte register reset value: 00h por enable/disable 01011010: por disable o thers: por enable note : it is recommended to disable the por . when por is enabled, current consumption is increased and, the lvr(low voltage reset) is ignored even the lvr is enabled by the ? rom option ? . 20.6 low voltage reset the low voltage reset occurs the reset event when current vdd is going down under the lvr level. it is configurable by the rom - option. ( see ? 8 . rom option ? on page 33 ) if you want to know more detail timing information , s ee ? 7.8 lvr (low v o ltage r e set) electrical characteristics ? on page 24 . figure 20 - 4 lvr timing diagram at 4mhz system clock
mc81f4 104 90 october 19, 2009 ver. 1.35 21. power down operation in the power - down mode s , power consumption is reduced considerably. for applications where power consumption is a critical factor, device provides two kinds of power saving functions, stop mode and sleep mode. table 21 - 1 on page 95 shows the status of each power saving mode. sleep mode is entered by the sscr register to 0fh. and stop mode is entered by stop instruction after the sscr register to 5ah. 21.1 sleep mode in this mode, the internal oscillation circui ts remain active. oscillation continues and peripherals are operate d normally but cpu stops. movement of all peripherals is shown in table 21 - 1 on page 95 . sleep mode is entered by setting the sscr register to 0fh. it is released by reset o r interrupt. to be released by interrupt, interrupt should be enabled before sleep mode. sscr stop and sleep control register 00f5h 7 6 5 4 3 2 1 0 sscr o ne byte register reset value: 00h w w w w w w w w it is used to set the stop or sleep mode. 5ah : stop 0fh : sleep note : to get into stop mode, sscr must be set to 5ah just before stop instruction execution. at stop mode, stop & sleep control register (sscr) value is cleared automatically when released. to get into sleep mode, sscr must be set to 0fh . release the sleep mode the exit from sleep mode is hardware reset or all interrupts. reset re - defines all the control registers but does not change the on - chip ram. (be careful, if the code is compiled with ram clear option , ram is cleared after reset by ram clear routine. it is possible to disable the ram clear option by option menu) . interrupts allow both on - chip ram and control registers to retain their values . if i - flag = 1, the normal interrupt response takes place. if i - flag = 0, the chip will resume execution starting with the instruction following the sleep instruction. it will not vector to interrupt service routine. (refer to figure 21 - 3 ) when exit from sleep mode by reset, enough oscillation stabilization time is required to normal operation. figure 21 - 2 shows the timing diagram. when released from the sleep mode, the basic interval timer is activated on wake - up. it is increased from 00 h until ff h . the count overflow is set to start normal op eration.
mc81f4 104 october 19, 2009 ver. 1.35 91 note : after sleep mode, at least one or more nop instruction for data bus pre - charge time should be written. ldm sscr,#0fh nop ;for data bus pre - charge time nop ;for data bus pre - charge time figure 21 - 1 sleep mode release timing by external interrupt figure 21 - 2 timing of sleep mode release by reset
mc81f4 104 92 october 19, 2009 ver. 1.35 21.2 stop mode in the stop mode, the main oscillator, system clock and peripheral clock is stopped. with the clock frozen, all functions are stopped, but the on - chip ram and control registers are held. the port pins out the values held by their respective port data register, port direction registers. oscillator stops and the systems internal operations are all held up. the states of the ram, registers, and latches valid immediately before the system is put in the stop state are all held. the program counter s top the address of the instruction to be executed after the instruction "stop" which starts the stop operating mode. note : the stop mode is activated by execution of stop instruction after setting the sscr to 5a h . (this register should be written by byte operation. if this register is set by bit manipulation instruction, for example "set1" or "clr1" instruction, it may be undesired operation) in the stop mode of operation, v dd can be reduced to minimize power consumption. care must be taken, however, to ensure that v dd is not reduced before the stop mode is invoked, and that v dd is restored to its normal operating level, before the stop mode is terminated. the reset should not be activated before v dd is restored to its normal operating level, and must be held active long enough to allow the oscillator to restart and stabilize. note : after stop instruction, at least two or more nop instruction should be written. ex) ldm ckctlr,#0fh ;more than 20ms ldm sscr,#5ah stop nop ;for stabilization time nop ;for stabilization time in the stop operation, the dissipation of the power associated with the oscillator and the internal hardware is lowered; however, the power dissipation associated with the pin interface (depending on the external circuitry and program) is not directly determined by the hardware operation of the stop feature. this point should be little current flows when the input level is stable at the power voltage level (v dd /v ss ); however, when the input level gets higher than the power voltage level (by approximately 0.3 to 0.5v), a current begins to flow. therefore, if cutting off the output transistor at an i/o port puts the p in signal into the high - impedance state, a current flow across the ports input transistor, requiring to fix the level by pull - up or other means.
mc81f4 104 october 19, 2009 ver. 1.35 93 release the stop mode the source for exit from stop mode is hardware reset, external interrupt, timer(ec 2 , 3 ) . reset re - defines all the control registers but does not change the on - chip ram. external interrupts allow both on - chip ram and control registers to retain their values. if i - flag = 1, the normal interrupt response takes place. if i - flag = 0, the chip will resume execution starting with the instruction following the stop instruction. it will not vector to interrupt service routine. (refer to figure 21 - 3 ) when exit from stop mode by external interrupt, enough oscillation stabilization time is required to normal operation. figure 21 - 4 shows the timing diagram. when released from the stop mode, the basic interval timer is activated on wake - up. it is increased from 00 h until ff h . the count overflow is set to start normal operation. therefore, before stop instruction, user must be set its relevant prescaler divide ratio to have long enough time (more than 20msec). this guarantees that oscillator has started and stabilized. by reset, exit from stop mode is shown in figure 21 - 5 . figure 21 - 3 stop releasing flow by interrupts
mc81f4 104 94 october 19, 2009 ver. 1.35 before executing stop instruction, basic interval timer must be set properly by software to get stabilization time which is longer than 20m s. figure 21 - 4 stop mode release timing by external interrupt figure 21 - 5 timing of stop mode release by reset
mc81f4 104 october 19, 2009 ver. 1.35 95 21.3 sleep vs stop peripheral stop mode sleep mode cpu stop stop ram retain retain basic interval timer stop operates continuously watchdog timer stop operates continuously timer/counter stop ( t he event counter can operate normally ) operates continuously buzzer, adc stop operates continuously main oscillator stop oscillation i/o ports retain retain control registers retain retain prescaler retain retain address data bus retain retain release source reset, timer(ec 2 /3 ) , external interrupt reset, all interrupts table 21 - 1 peripheral operation during power saving mode
mc81f4 104 96 october 19, 2009 ver. 1.35 21.4 changing the stabilizing time after reset or wake up from the stop/sleep mode, there is a stabilizing time to make sure the system oscillation is stabilized . a ctually the stabilizing time is the basic interval timer ? s one cycle time. so it is adjustable by changing the basic interval timer ? s clock division.( see chapter ? 14 . b asic i nterval t imer ? at page 68 to know how to change the basic interval timer ? s clock division.) it is useful to reduce the power consumption in battery operation with stop/sleep mode. in the battery operation, reducing n ormal operation time is the key - point to reducing the power consumption. note that, it is not possible after reset. because after reset, the control registers are initialized. 21.5 minimizing current consumption the stop mode is designed to reduce power consumption. to minimize current drawn during stop mode, the user should turnoff output drivers that are sourcing or sinking current, if it is practical. when port is configured as an input, input level should be clos ed to 0v or 5v to avoid power consumption. figure 21 - 6 application example of unused input port
mc81f4 104 october 19, 2009 ver. 1.35 97 in the left case, much current flows from port to gnd. in the left case, tr. base current flows from port to gnd. to avoid power consumption, there should be low output to the port . note : in the stop operation, the power dissipation associated with the oscillator and the internal hardware is lowered; however, the power dissipation associated with the pin interface (depending on the external circuitry and program) is not directly determined by the hardware operation of the stop feature. this point should be little current flows when the input level is stable at the power voltage level (v dd /v ss ); however, when the input level becomes higher than the power voltage level (by approximately 0.3v), a current begins to flow. therefore, if cutting off the output transistor at an i/o port puts the pin signal into the high impedance state, a current flow across the ports input transistor, requiring it to fix the level by pull - up or other means. it should be set properly in order that current flow through port doesn't exist. first consider the port setting to input mode. be sure that there is circuit. in input mode, the pin impedance viewing from external mcu is very high that the current doesn?t flow. but input voltage level shou ld be v ss or v dd . be careful that if unspecified voltage, i.e. if uncertain voltage level (not v ss or v dd ) is applied to input pin, there can be little current (max. 1ma at around 2v) flow. if it is not appropriate to set as an input mode, then set to outp ut mode considering there is no current flow. the port setting to high or low is decided by considering its relationship with external circuit. for example, if there is external pull - up resistor then it is set to output mode, i.e. to high, and if there is external pull - down register, it is set to low. figure 21 - 7 application example of unused output port
mc81f4 104 98 october 19, 2009 ver. 1.35 22. emulator
mc81f4 104 october 19, 2009 ver. 1.35 99 mark name description C C C C C C C C C C x1 a crystal/resonator socket c11 a capacitor socket for crystal c12 a capacitor socket for crystal r8 register socket for external rc oscillator
mc81f4 104 100 october 19, 2009 ver. 1.35 mark name description sw2 C ? v_user a connector for power source which can be used for eva.board. j_usera a connecter for target system. note : only gnd is connected between eva.board and target system. vdd is not connected. so, the target system is required it ? s own power source. using ? v_user ? is not recommended . it ? s own power source is more stable. besides, choice - dr can change the vdd level it self. there is a switch which changes the vdd level at the bottom of the choice - dr hardware.(but old version of choice - dr hardware dose not support it)
mc81f4 104 october 19, 2009 ver. 1.35 101 23. in system programm ing 23.1 getting started the in - system programming (isp) is an ability to program the code into the mcu while it is installed in a complete system. usb_sio_isp uses both usb to communicate with pc and sio to communicate with mcu. that is why we call it as ? usb_sio_isp ? . in fact there are another isp types. so remember that all mc81f4xxx series use ? usb_sio_isp ? . here is a procedure to use isp. 1. power off the target system. if you use the reset/vpp pin as an output mode, power on timing is very important . so you must read ? entering isp mode at power on time ? and strictly obey the procedure. 2. install the usb_sio_isp software. (it is required at only first time) 1) download the isp software from http://www.abov.co.kr 2) unzip the downloaded file and connect the usb_sio_isp board. 3) install the driver for usb_sio_isp. (there is a driver file in the zip file.) 3. make sure the hardware condition is satisfied. and connect the isp cable. see ? 23.3 hardware conditions to enter the isp mode ? page 104 , 4. run the software and select a device. all commands are enabled after select the device. 5. power on the target system. if you use the reset/vpp pin as an input mode, powe r on timing is not that important. but make sure the power is turned - on before execute the isp commands. 6. execute isp commands as you want. if you want to write a code into your mcu, it is recommendable to do following step. ? load file ? - > ? auto ? ( while ? auto option write ? and ? auto show option ? options are enabled ). after finish an isp command is executed, the mcu enters to normal operation mode automatically. so you can see the system is working right after the isp command is finished. ( ? auto ? is assumed as one command ? ) in fact, it is possible to repeat the step - 6 until the hardware condition is changed. b ut in case of reset/vpp pin is used as an output mode, do not repeat step - 6. in that case, you must follow the procedure. see ? entering isp mode at power on time ? for more information . after you change the ? rom option ? , you must do power - off and power - on to reflect the changed ? rom option ? , even you can repeat the step - 6 and see the changed code ? s operation without doing it. the mcu reads the ? rom option ? when only the ? power on reset time ? .
mc81f4 104 102 october 19, 2009 ver. 1.35 23.2 basic isp s/w information the figure 23 - 1 is the usb_sio_ isp software based on ms - windows. this software support s only sio _isp type devices . function description load file load the data from the selected file storage into the memory buffer. save file save the current data in your memory buffer to a disk storage by using the intel motorola hex format. blank check verify whether or not a device is in an erased or unprogrammed state. program this button enables you to place new data from the memory buffer into the target device. program write the current data into the mcu. read read the data in the target mcu into the buffer for examination. the checksum will be displayed on the checksum box. figure 23 - 1 isp software
mc81f4 104 october 19, 2009 ver. 1.35 103 verify assures that data in the de vice matches data in the memory buffer. if your device is secured, a verification error is detected. erase erase the data in your target mcu before programming it. option selection set the configuration data of target mcu. the security locking is set with this button. option write progam the configuration data of target mcu. the security locking is performed with this button. auto following sequence is performed ; 1.erase 2.program 3.verify 4.option write auto option write enable the option writing when the ? ? ? ? ? ? ? ? note: mcu configuration value is erased after erase operation. it must be configured to match with user target board. otherwise, it is failed to enter isp mode, or its operation is not desirable.
mc81f4 104 104 october 19, 2009 ver. 1.35 23.3 hardware conditions to enter the isp mode anytime r e s e t/ vpp pin goes +9v , the mcu entering an isp mode except reset/vpp pin is output mode(see note1). 1. if other signals affect sio communic a tion in isp mode, disconnect these pins by using a jumper or a switch. n ote: 1) u sing reset/vpp pin as an output mode is not recommended even it is possible. anytime reset/vpp pin goes +9v, the mcu entering an isp mode except reset/vpp pin is output mode. if it is output mode, +9v signal is clashing with the output voltage. so if reset/vpp pin is used as an output mode, do not try to execute any isp commands when mcu is in normal operation mode. i t is allowable when only power on time. see ? entering isp mode at power on time ? for more information . 2) there is a 10k ? pull - down register at vpp pin in the isp board. that is why 75k ? register is suggested for r/c reset circuit. so those two register makes a voltage divider circuit when isp board is connected. so the vpp level can ? t go down to low level status if the register of reset circuit value is too small. otherwise, if the register value is too large the capacitor value also changed and the reset circuit ? s char acteristic s also changed. figure 23 - 2 hardware conditions to enter the isp mode reset/vpp sdata sclk gnd xout vdd xin 7 5 3 1 9 8 6 4 2 1 0 0.1uf 75k ?
mc81f4 104 october 19, 2009 ver. 1.35 105 23.4 entering isp mode at power on time basically anytime +9v signal is forced to reset/vpp pin, the mcu is entering into isp mode. but it makes trouble when the reset/vpp pin is output mode. because the +9v signal is clashing with the port ? s output voltage. but it is possible to enter the isp mode at the power on time even reset/vpp pin is used as an output mode. there is an oscillator stabilizing time when power is turn on. while in the time reset/vpp pin is in input mode even it is used as an output mode in operation time. a proper procedure is required to make sure that isp board catch the oscillator stabilizing time to enter the isp mode. see following procedure. 1. power off the target system. 2. configure the target system as isp mode. 3. attach a isp b/d into the target system. 4. run the isp s/w 5. select the target device. 6. power on the target system. 7. execute isp commands as you want. note : power on the target system after select the target device is essential. because when target device is selected, isp board is getting ready to catch the proper timing to rise the vpp (+9v) signal.
mc81f4 104 106 october 19, 2009 ver. 1.35 23.5 usb - sio - isp board figure 23 - 3 usb - sio - isp board connect usb - mini type cable
mc81f4 104 october 19, 2009 ver. 1.35 107 24. instruction set 24.1 terminology list a accumulator x x - register y y - register psw program status word #imm 8 - bit immediate data dp direct page offset address !abs absolute address [ ] indirect expression { } register indirect expression { }+ register indirect expression, after that, register auto - increment .bit bit position a.bit bit position of accumulator dp.bit bit position of direct page memory m.bit bit position of memory data (000h~0fffh) rel relative addressing data upage u - page (0ff00h~0ffffh) offset address n table call number (0~15) + addition x upper nibble expression in opcode when it is even number (bit7~bit5, bit4=0) y upper nibble expression in opcode when it is odd number (bit7~bit5, bit4=1) ? subtraction ? multiplication ? division ( ) contents expression and or ? exclusive or ~ not assignment / transfer / shift left shift right bit position 1 bit position 0
mc81f4 104 108 october 19, 2009 ver. 1.35 ? exchange = equal not equal 24.2 instruction map low high 00000 00 00001 01 00010 02 00011 03 00100 04 00101 05 00110 06 00111 07 01000 08 01001 09 01010 0a 01011 0b 01100 0c 01101 0d 01110 0e 01111 0f 000 - set1 dp.bit bbs a.bit,rel bbs dp.bit,rel adc #imm adc dp adc dp+x adc !abs asl a asl dp tcall 0 seta1 .bit bit dp pop a push a brk 001 clrc ? ? ? sbc #imm sbc dp sbc dp+x sbc !abs rol a rol dp tcall 2 clra1 .bit com dp pop x push x bra rel 010 clrg ? ? ? cmp #imm cmp dp cmp dp+x cmp !abs lsr a lsr dp tcall 4 not1 m.bit tst dp pop y push y pcall upage 011 di ? ? ? or #imm or dp or dp+x or !abs ror a ror dp tcall 6 or1 or1b cmpx dp pop psw push psw ret 100 clrv ? ? ? and #imm and dp and dp+x and !abs inc a inc dp tcall 8 and1 and1b cmpy dp cbne dp+x txsp inc x 101 setc ? ? ? eor #imm eor dp eor dp+x eor !abs dec a dec dp tcall 10 eor1 eor1b dbne dp xma dp+x tspx dec x 110 setg ? ? ? lda #imm lda dp lda dp+x lda !abs txa ldy dp tcall 12 ldc ldcb ldx dp ldx dp+y xcn das (n/a) 111 ei ? ? ? ldm dp,#imm sta dp sta dp+x sta !abs tax sty dp tcall 14 stc m.bit stx dp stx dp+y xax stop low high 10000 10 10001 11 10010 12 10011 13 10100 14 10101 15 10110 16 10111 17 11000 18 11001 19 11010 1a 11011 1b 11100 1c 11101 1d 11110 1e 11111 1f 000 bpl rel clr1 dp.bit bbc a.bit,rel bbc dp.bit,rel adc {x} adc !abs+y adc [dp+x] adc [dp]+y asl !abs asl dp+x tcall 1 jmp !abs bit !abs addw dp ldx #imm jmp [!abs] 001 bvc rel ? ? ? sbc {x} sbc !abs+y sbc [dp+x] sbc [dp]+y rol !abs rol dp+x tcall 3 call !abs test !abs subw dp ldy #imm jmp [dp] 010 bcc rel ? ? ? cmp {x} cmp !abs+y cmp [dp+x] cmp [dp]+y lsr !abs lsr dp+x tcall 5 mul tclr1 !abs cmpw dp cmpx #imm call [dp] 011 bne rel ? ? ? or {x} or !abs+y or [dp+x] or [dp]+y ror !abs ror dp+x tcall 7 dbne y cmpx !abs ldya dp cmpy #imm reti 100 bmi rel ? ? ? and {x} and !abs+y and [dp+x] and [dp]+y inc !abs inc dp+x tcall 9 div cmpy !abs incw dp inc y tay 101 bvs rel ? ? ? eor {x} eor !abs+y eor [dp+x] eor [dp]+y dec !abs dec dp+x tcall 11 xma {x} xma dp decw dp dec y tya 110 bcs rel ? ? ? lda {x} lda !abs+y lda [dp+x] lda [dp]+y ldy !abs ldy dp+x tcall 13 lda {x}+ ldx !abs stya dp xay daa (n/a) 111 beq rel ? ? ? sta {x} sta !abs+y sta [dp+x] sta [dp]+y sty !abs sty dp+x tcall 15 sta {x}+ stx !abs cbne dp xyx nop
mc81f4 104 october 19, 2009 ver. 1.35 109 24.3 instruction set arithmetic / logic no. mnemonic op code byte no cycle no operation flag nvgbhizc 1 adc #imm 04 2 2 add with carry. a ? ( a ) + ( m ) + c nv -- h - zc 2 adc dp 05 2 3 3 adc dp + x 06 2 4 4 adc !abs 07 3 4 5 adc !abs + y 15 3 5 6 adc [ dp + x ] 16 2 6 7 adc [ dp ] + y 17 2 6 8 adc { x } 14 1 3 9 a nd #imm 8 4 2 2 logical and a ? ( a ) ( m ) n - -- - - z - 10 a nd dp 8 5 2 3 11 a nd dp + x 8 6 2 4 12 a nd !abs 8 7 3 4 13 a nd !abs + y 9 5 3 5 14 a nd [ dp + x ] 9 6 2 6 15 a nd [ dp ] + y 9 7 2 6 16 a nd { x } 9 4 1 3 17 asl a 08 1 2 arithmetic shift left n - -- - - z c 18 asl dp 09 2 4 19 asl dp + x 19 2 5 20 asl !abs 18 3 5 21 cmp #imm 4 4 2 2 compare accumulator contents with memory contents ( a ) - ( m ) n - -- - - z c 22 cmp dp 4 5 2 3 23 cmp dp + x 4 6 2 4 24 cmp !abs 4 7 3 4 25 cmp !abs + y 5 5 3 5 26 cmp [ dp + x ] 5 6 2 6 0 c 7 6 5 4 3 2 1 0
mc81f4 104 110 october 19, 2009 ver. 1.35 no. mnemonic op code byte no cycle no operation flag nvgbhizc 27 cmp [ dp ] + y 5 7 2 6 28 cmp { x } 54 1 3 29 cmpx #imm 5e 2 2 compare x contents with memory contents ( x ) - ( m ) n - -- - - z c 30 cmpx dp 6c 2 3 31 cmpx !abs 7c 3 4 32 cmpy #imm 7e 2 2 compare y contents with memory contents ( y ) - ( m ) n - -- - - z c 33 cmpy dp 8c 2 3 34 cmpy !abs 9c 3 4 35 com dp 2c 2 4 1 ? s complement : ( dp ) ? ~( dp ) n - -- - - z - 36 daa - - - unsupported - 37 das - - - unsupported - 38 dec a a8 1 2 decrement m ? ( m ) - 1 n - -- - - z - 39 dec dp a9 2 4 40 dec dp + x b9 2 5 41 dec !abs b8 3 5 42 dec x af 1 2 43 dec y be 1 2 44 div 9b 1 12 divide : ya/x q:a, r:y n v -- h - z - 45 eor #imm a 4 2 2 exclusive or a ? ( a ) ? ( m ) n - -- - - z - 46 eor dp a 5 2 3 47 eor dp + x a 6 2 4 48 eor !abs a 7 3 4 49 eor !abs + y b 5 3 5 50 eor [ dp + x ] b 6 2 6 51 eor [ dp ] + y b 7 2 6 52 eor { x } b 4 1 3 53 inc a 88 1 2 increment m ? ( m ) + 1 n - -- - - z - 54 inc dp 89 2 4
mc81f4 104 october 19, 2009 ver. 1.35 111 no. mnemonic op code byte no cycle no operation flag nvgbhizc 55 inc dp + x 99 2 5 56 inc !abs 98 3 5 57 inc x 8f 1 2 58 inc y 9e 1 2 59 lsr a 48 1 2 arithmetic shift left n - -- - - z c 60 lsr dp 49 2 4 61 lsr dp + x 59 2 5 62 lsr !abs 58 3 5 63 mul 5b 1 9 multiply : ya ? y ? a n - -- - - z - 64 or #imm 6 4 2 2 logical or a ? ( a ) ( m ) n - -- - - z - 65 or dp 6 5 2 3 66 or dp + x 6 6 2 4 67 or !abs 6 7 3 4 68 or !abs + y 7 5 3 5 69 or [ dp + x ] 7 6 2 6 70 or [ dp ] + y 7 7 2 6 71 or { x } 7 4 1 3 72 rol a 28 1 2 rotate left through carry n - -- - - z c 73 rol dp 29 2 4 74 rol dp + x 39 2 5 75 rol !abs 38 3 5 76 ror a 68 1 2 rotate right through carry n - -- - - z c 77 ror dp 69 2 4 78 ror dp + x 79 2 5 79 ror !abs 78 3 5 80 sbc #imm 2 4 2 2 subtract with carry a ? ( a ) - ( m ) - ~( c ) n v - - h z c 81 sbc dp 2 5 2 3 82 sbc dp + x 2 6 2 4 7 6 5 4 3 2 1 0 c c 7 6 5 4 3 2 1 0 0 7 6 5 4 3 2 1 0 c
mc81f4 104 112 october 19, 2009 ver. 1.35 no. mnemonic op code byte no cycle no operation flag nvgbhizc 83 sbc !abs 2 7 3 4 84 sbc !abs + y 3 5 3 5 85 sbc [ dp + x ] 3 6 2 6 86 sbc [ dp ] + y 3 7 2 6 87 sbc { x } 3 4 1 3 88 tst dlp 4c 2 3 test memory contents for negative or zero ( dp ) C 00h n - -- - - z - 89 xcn ce 1 5 exchange nibbles within the accumulator a7~a4 ? a3~a0 n - -- - - z -
mc81f4 104 october 19, 2009 ver. 1.35 113 register / memory operation no. mnemonic op code byte no cycle no operation flag nvgbhizc 1 lda #imm c 4 2 2 load accumulator a ? ( m ) n - -- - - z - 2 lda dp c 5 2 3 3 lda dp + x c 6 2 4 4 lda !abs c 7 3 4 5 lda !abs + y d 5 3 5 6 lda [ dp + x ] d 6 2 6 7 lda [ dp ] + y d 7 2 6 8 lda { x } d 4 1 3 9 lda { x } + db 1 4 x - register auto - increment : a ? ( m ) , x ? x + 1 10 ldm dp, #imm e4 3 5 load memory with immediate data : ( m ) ? imm -- -- - - -- 11 ldx #imm 1e 2 2 load x - register x ? ( m ) n - -- - - z - 12 ldx dp cc 2 3 13 ldx dp + y cd 2 4 14 ldx !abs dc 3 4 15 ldy #imm 3e 2 2 load y - register y ? ( m ) n - -- - - z - 16 ldy dp c9 2 3 17 ldy dp + y d9 2 4 18 ldy !abs d8 3 4 19 sta dp e 5 2 4 store accumulator contents in memory ( m ) ? a -- -- - - -- 20 sta dp + x e 6 2 5 21 sta !abs e 7 3 5 22 sta !abs + y f 5 3 6 23 sta [ dp + x ] f 6 2 7 24 sta [ dp ] + y f 7 2 7 25 sta { x } f4 1 4 26 sta { x }+ fb 1 4 x - register auto - increment : ( m ) ? a, x ? x + 1
mc81f4 104 114 october 19, 2009 ver. 1.35 no. mnemonic op code byte no cycle no operation flag nvgbhizc 27 stx dp ec 2 4 store x - register contents in memory ( m ) ? x -- -- - - -- 28 stx dp + y ed 2 5 29 stx !abs fc 3 5 30 sty dp e9 2 4 store y - register contents in memory ( m ) ? y -- -- - - -- 31 sty dp + x f9 2 5 32 sty !abs f8 3 5 33 tax e8 1 2 transfer accumulator contents to x - register : x ? a n - -- - - z - 34 tay 9f 1 2 transfer accumulator contents to y - register : y ? a n - -- - - z - 35 tspx ae 1 2 transfer stack - pointer contents to x - register : x ? sp n - -- - - z - 36 txa c8 1 2 transfer x - register contents to accumulator : a ? x n - -- - - z - 37 txsp 8e 1 2 transfer x - register contents to stack - pointer : sp ? x n - -- - - z - 38 tya bf 1 2 transfer y - register contents to accumulator : a ? y n - -- - - z - 39 xax ee 1 4 exchange x - register contents with accumulator : x ? a -- -- - - -- 40 xay de 1 4 exchange y - register contents with accumulator : y ? a -- -- - - -- 41 xma dp bc 2 5 exchange memory contents with accumulator : ( m ) ? a n - -- - - z - 42 xma dp + x ad 2 6 43 xma {x} bb 1 5 44 xyx fe 1 4 exchange x - register contents with y - register : x ? y -- -- - - --
mc81f4 104 october 19, 2009 ver. 1.35 115 16 bit manipulation no. mnemonic op code byte no cycle no operation flag nvgbhizc 1 addw dp 1d 2 5 16 - bits add without carry ya ? ( ya ) + ( dp + 1 ) ( dp ) n v -- h - z c 2 cmpw dp 5d 2 4 compare ya contents with memory pair contents : ( ya ) - ( dp + 1 ) ( dp ) n - -- - - z c 3 decw dp bd 2 6 decrement memory pair ( dp + 1 ) ( dp ) ? ( dp + 1 ) ( dp ) C 1 n - -- - - z - 4 incw dp 9d 2 6 inc rement memory pair ( dp + 1 ) ( dp ) ? ( dp + 1 ) ( dp ) + 1 n - -- - - z - 5 ldya dp 7d 2 5 load ya ya ? ( dp + 1 ) ( dp ) n - -- - - z - 6 stya dp dd 2 5 store ya ( dp + 1 ) ( dp ) ? ya -- -- - - -- 7 subw dp 3d 2 5 16 - bits subtract without carry ya ? ( ya ) - ( dp + 1 ) ( dp ) n v -- h - z c
mc81f4 104 116 october 19, 2009 ver. 1.35 bit manipulation no. mnemonic op code byte no cycle no operation flag nvgbhizc 1 and1 m.bit 8b 3 4 bit and c - flag : c ? ( c ) ( m.bit ) -- -- - - - c 2 and1 b m.bit 8b 3 4 bit and c - flag and not : c ? ( c ) ~( m.bit ) -- -- - - - c 3 bit dp 0c 2 4 bit test a with memory : z ? ( a ) ( m ), n ? ( m7 ), v ? ( m6 ) mm -- - - z - 4 bit !abs 1c 3 5 5 clr 1 dp .bit y1 2 4 clear bit : ( m.bit ) ? 0 -- -- - - -- 6 clra 1 a .bit 2b 2 2 clear a bit : ( a.bit ) ? 0 -- -- - - -- 7 clrc 20 1 2 clear c - flag : c ? 0 -- -- - - - 0 8 clrg 40 1 2 clear g - flag : g ? 0 -- 0 - - - -- 9 clrv 80 1 2 clear v - flag : v ? 0 - 0 - - 0 - -- 10 eor 1 m.bit ab 3 5 bit exclusive - or c - flag : c ? ( c ) ? ( m.bit ) -- -- - - - c 11 eor 1 b m.bit ab 3 5 bit exclusive - or c - flag and not : c ? ( c ) ? ~( m.bit ) -- -- - - - c 12 ldc m.bit cb 3 4 load c - flag : c ? ( m.bit ) -- -- - - - c 13 ldcb m.bit cb 3 4 load c - flag with not : c ? ~( m.bit ) -- -- - - - c 14 not 1 m .bit 4b 3 5 bit complement : ( m.bit ) ? ~( m.bit ) -- -- - - -- 15 or 1 m .bit 6b 3 5 bit or c - flag : c ? c ( m.bit ) -- -- - - - c 16 or 1 b m .bit 6b 3 5 bit or c - flag and not : c ? c ~ ( m.bit ) -- -- - - - c 17 set 1 dp .bit x1 2 4 set bit : ( m.bit ) ? 1 -- -- - - -- 18 seta 1 a .bit 0b 2 2 set a bit : ( a.bit ) ? 1 -- -- - - -- 19 setc a0 1 2 set c - flag : c ? 1 -- -- - - - 1 20 setg c0 1 2 set g - flag : g ? 1 -- 1 - - - -- 21 stc m.bit eb 3 6 store c - flag : ( m.bit ) ? c -- -- - - -- 22 tclr 1 !abs 5c 3 6 test and clear bits with a : a C ( m ), ( m ) ? ( m ) ~( a ) n - -- - - z - 23 tset 1 !abs 3c 3 6 test and set bits with a : a C ( m ), ( m ) ? ( m ) ( a ) n - -- - - z -
mc81f4 104 october 19, 2009 ver. 1.35 117 branch / jump no. mnemonic op code byte no cycle no operation flag nvgbhizc 1 bbc a .bit , rel y2 2 4/6 branch if bit clear : if ( bit ) = 0, then pc ? ( pc ) + rel -- -- - - -- 2 bbc dp .bit , rel y3 3 5/7 3 bbs a .bit , rel x2 2 4/6 branch if bit set : if ( bit ) = 1, then pc ? ( pc ) + rel -- -- - - -- 4 bbs dp .bit , rel x3 3 5/7 5 bcc rel 50 2 2/4 branch if carry bit clear : if ( c ) = 0, then pc ? ( pc ) + rel -- -- - - -- 6 bc s rel d0 2 2/4 branch if carry bit set : if ( c ) = 1, then pc ? ( pc ) + rel -- -- - - -- 7 beq rel f0 2 2/4 branch if equal : if ( z ) = 1, then pc ? ( pc ) + rel -- -- - - -- 8 bmi rel 90 2 2/4 branch if minus : if ( n ) = 1, then pc ? ( pc ) + rel -- -- - - -- 9 bne rel 70 2 2/4 branch if not equal : if ( z ) = 0, then pc ? ( pc ) + rel -- -- - - -- 10 bpl rel 10 2 2/4 branch if plus : if ( n ) = 0, then pc ? ( pc ) + rel -- -- - - -- 11 bra rel 2f 2 4 branch always : pc ? ( pc ) + rel -- -- - - -- 12 b v c rel 30 2 2/4 branch if overflow bit clear : if ( v ) = 0, then pc ? ( pc ) + rel -- -- - - -- 13 b vs rel b0 2 2/4 branch if overflow bit set : if ( v ) = 1, then pc ? ( pc ) + rel -- -- - - -- 14 call !abs 3b 3 8 subroutine call m( sp ) ? ( pch ), sp ? sp C 1, m( sp ) ? ( pcl ), sp ? sp C 1, i f !abs, pc ? abs ; if [dp], pcl ? ( dp ), pch ? ( dp + 1 ) -- -- - - -- 15 call [dp] 5f 2 8 16 cbne dp, rel fd 3 5/7 compare and branch if not equal : if ( a ) ( m ), then pc ? ( pc ) + rel -- -- - - -- 17 cbne dp+x , rel 8d 3 6/8 18 d bne dp, rel ac 3 5/7 decrement and branch if not equal : if ( m ) 0, then pc ? ( pc ) + rel -- -- - - -- 19 d bne y , rel 7b 2 4/6 20 jmp !abs 1b 3 3 unconditional jump : pc ? jump address -- -- - - -- 21 jmp [!abs] 1f 3 5 22 jmp [dp] 3f 2 4 23 pcall upage 4f 2 6 u - page call m( sp ) ? ( pch ), sp ? sp C 1, -- -- - - --
mc81f4 104 118 october 19, 2009 ver. 1.35 no. mnemonic op code byte no cycle no operation flag nvgbhizc m( sp ) ? ( pcl ), sp ? sp C 1, pcl ? ( upage ), pch ? 0ffh 24 tcall n na 1 8 table call m( sp ) ? ( pch ), sp ? sp C 1, m( sp ) ? ( pcl ), sp ? sp C 1, pcl ? ( table vector l ), pch ? (table vector h ) -- -- - - -- control operation / etc no. mnemonic op code byte no cycle no operation flag nvgbhizc 1 brk 0f 1 8 software interrupt : b ? 1 , m( sp ) ? ( pch ), sp ? sp C 1, m( sp ) ? ( pcl ), sp ? sp C 1, m( sp ) ? ( psw ), sp ? sp C 1, pcl ? ( 0ffdeh ), pch ? ( 0ffdfh ) -- - 1 - 0 -- 2 di 60 1 3 disable interrupt : i ? 0 -- -- - 0 -- 3 ei e0 1 3 enable interrupt : i ? 1 -- -- - 1 -- 4 nop ff 1 2 no operation -- -- ---- 5 pop a 0d 1 4 sp ? sp + 1, a ? m( sp ) sp ? sp + 1, x ? m( sp ) sp ? sp + 1, y ? m( sp ) sp ? sp + 1, psw ? m( sp ) -- -- - - -- 6 pop x 2d 1 4 7 pop y 4d 1 4 8 pop psw 6d 1 4 restored 9 push a 0e 1 4 m( sp ) ? a, sp ? sp - 1 m( sp ) ? x, sp ? sp - 1 m( sp ) ? y, sp ? sp - 1 m( sp ) ? psw, sp ? sp - 1 -- -- - - -- 10 push x 2e 1 4 11 push y 4e 1 4 12 push psw 6e 1 4 13 ret 6f 1 5 return from subroutine sp ? sp + 1, pcl ? m( sp ), sp ? sp + 1, pch ? m( sp ) -- -- - - -- 14 reti 7f 1 6 return from interrupt sp ? sp + 1, psw ? m( sp ), sp ? sp + 1, pcl ? m( sp ), sp ? sp + 1, pch ? m( sp ) restored 15 stop ef 1 3 stop mode ( halt cpu, stop oscillator ) -- -- - - --

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